- 您現(xiàn)在的位置：買賣IC網 > PDF目錄371872 > HN58V65ATI-10 (Renesas Technology Corp.) 64k EEPROM (8-kword x 8-bit) Ready/Busy function, RES function (HN58V66A) Wide Temperature Range version PDF資料下載
參數(shù)資料
| 型號： | HN58V65ATI-10 |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | 64k EEPROM (8-kword x 8-bit) Ready/Busy function, RES function (HN58V66A) Wide Temperature Range version |
| 中文描述： | 64K的EEPROM的（8 KWord的× 8位）就緒/忙功能水庫功能（HN58V66A）寬溫版本 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 225K |
| 代理商： | HN58V65ATI-10 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
HN58V65AI/HN58V66AI/HN58V65A-SR/HN58V66A-SR Series
Rev.3.00, Feb.02.2004, page 10 of 26
Write Cycle 2
(4.5
≤
V
CC
≤
5.5 V)
Parameter
Symbol Min
*
3
Typ
Max
Unit
Test conditions
Address setup time
t
AS
0
30
10
*
4
ns
Address hold time
CE
to write setup time (
WE
controlled)
CE
hold time (
WE
controlled)
WE
to write setup time (
CE
controlled)
WE
hold time (
CE
controlled)
OE
to write setup time
OE
hold time
t
AH
50
ns
t
CS
0
ns
t
CH
0
ns
t
WS
0
ns
t
WH
0
ns
t
OES
0
ns
t
OEH
0
ns
Data setup time
t
DS
50
ns
Data hold time
WE
pulse width (
WE
controlled)
CE
pulse width (
CE
controlled)
t
DH
0
ns
t
WP
100
ns
t
CW
100
ns
Data latch time
t
DL
50
ns
μ
s
μ
s
ms
Byte load cycle
t
BLC
0.2
Byte load window
t
BL
100
120
0
*
5
Write cycle time
t
WC
Time to device busy
t
DB
ns
Write start time
Reset protect time
*
2
Reset high time
*
2, 6
Notes: 1. t
DF
and t
DFR
are defined as the time at which the outputs achieve the open circuit conditions and
are no longer driven.
2. This function is supported by only the HN58V66A.
3. Use this device in longer cycle than this value.
4. t
WC
must be longer than this value unless polling techniques or RDY/
Busy
are used. This device
automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t
DW
if polling techniques or RDY/
Busy
are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page address and these addresses are latched at the first falling edge of
WE
.
8. A6 through A12 are page address and these addresses are latched at the first falling edge of
CE
.
9. See AC read characteristics.
t
DW
ns
μ
s
μ
s
t
RP
100
t
RES
1
相關PDF資料 |
PDF描述 |
|---|---|
| HN58V65ATI-10E | 64k EEPROM (8-kword x 8-bit) Ready/Busy function, RES function (HN58V66A) Wide Temperature Range version |
| HN58X2464FPIAG | EEPROM |
| HN58X2402 | I2C Serial EEPROM |
| HN58X2402FP | I2C Serial EEPROM |
| HN58X2402SFPIAG | EEPROM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HN58V65ATI-10E | 制造商:Renesas Electronics Corporation 功能描述: |
| HN58V66A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
| HN58V66AFP-10 | 制造商:Renesas Electronics Corporation 功能描述:EEPROM PARALLEL 64KBIT 8KX8 3.3V/5V 28SOP - Rail/Tube |
| HN58V66AFP-10E | 制造商:Renesas Electronics Corporation 功能描述:EEPROM Parallel 64K-bit 8K x 8 3.3V/5V 28-Pin SOP |
| HN58V66AFPI-10 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:64k EEPROM (8-kword x 8-bit) Ready/Busy function, RES function (HN58V66A) Wide Temperature Range version |
發(fā)布緊急采購，3分鐘左右您將得到回復。