參數(shù)資料
型號(hào): HN29W256H02TE
廠商: Hitachi,Ltd.
英文描述: Controller for AND Flash Memory(AND型閃速存儲(chǔ)器控制器)
中文描述: 控制器及快閃記憶體(及型閃速存儲(chǔ)器控制器)
文件頁(yè)數(shù): 31/73頁(yè)
文件大小: 333K
代理商: HN29W256H02TE
HN29W256H02TE-1
Address Data 7
6
5
4
3
2
1
0
Description of contents
CIS function
100H
1BH CISTPL_CFTABLE_ENTRY
Configuration table entry
tuple
Tuple code
102H
0FH
TPL_LINK
Link length is 15 bytes
Link to next tuple
104H
C3H I
D Configuration INDEX
ATA secondary I/O mapped
configuration
I = 1: Interface byte follows
D = 1: default entry
Configuration index = 3
Configuration table index
byte TPCE_INDX
106H
41H
W
R P
B
Interface type
W = 0: Wait not used
R = 1: Ready active
P = 0: WP not used
B = 0: BVS1 and BVD2 not
used
IF type = 1: I/O interface
Interface description field
TPCE_IF
108H
99H
M
MS
IR IO T
P
M = 1: misc info present
MS = 00: No memory space
info
IR = 1: Interrupt info present
IO = 1: I/O port info present
T = 0: No timing info present
P = 1: V
CC
only info
Nominal voltage only follows
R: Reserved
DI: Power down Current info
PI: Peak current info
AI: Average current info
SI: Static current info
HV: Max voltage info
LV: Min voltage info
NV: Nominal voltage info
Feature selection byte
TPCE_FS
10AH
01H
R
DI PI AI SI HV LV NV
Power parameters for V
CC
10CH
55H
X
Mantissa
Exponent
Nominal voltage = 5 V
V
CC
nominal value
I/O space description field
TPCE_IO
10EH
EAH R
S
E
IO AddrLine
R = 1: Range follows
S = 1: 16-bit hosts supported
E = 1: 8-bit hosts supported
IO AddrLines: 10 lines
decoded
110H
61H
LS
AS
N range
LS = 1: Size of lengths is 1
byte
AS = 2: Size of address is 2
bytes
N Range = 1: Address range - 1
I/O range format description
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