參數(shù)資料
型號(hào)： HMS81C4360SK
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述： 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PDIP32
封裝： SKDIP-32
文件頁(yè)數(shù)： 41/94頁(yè)
文件大?。?/td> 1652K
代理商： HMS81C4360SK
HMS8132E/HMS81032TL
Nov. 2001 Ver 2.00
37
12. WATCH DOG TIMER
Watch Dog Timer (WDT) consists of 6-bit binary counter,
6-bit comparator, and Watch Dog Timer Register
(WDTR).Watch Dog Timer can be used 6-bit general Tim-
er or specific Watch dog timer by setting bit5 (WDTON)
of Clock Control Register (CKCTLR).By assigning
bit6(WDTCL) of WDTR, 6-bit counter can be cleared.
WDT Interrupt (IFWDT) interval is determined by the in-
terrupt IFBIT interval of Basic Interval Timer and the val-
ue of WDT Register.
-Interval of IFWDT = (IFBIT interval) * (WDTR value)
As IFBIT (Basic Interval Timer Interrupt Request) is used
for input clock of WDT, Input clock cycle is possible from
512 us to 65,536 us by BTS. (at fex = 4MHz)
*At Hardware reset time,WDT starts automatically.
Therefore the user must select the CKCTLR and WDTR
before WDT overflow.
-Reset WDTR value = 0F
h
,=15
-Interval of WDT = 65,536 * 15 = 983040 us
(about 1second)
Note:
When WDTR Register value is 63 (3Fh)
(Caution): Do not use “0” for WDTR Register value.
Device come into the reset state by WDT
Figure 12-1 Block diagram of Watch Dog Timer
IFWDT
WDT
INTERRUPT
WDTR (6-bit)
WDT (6-bit)
Comparator
7
-
6
5
4
3
2
1
0
INITIAL VALUE: -0001111
b
ADDRESS: 0C8
H
WDTR
WDTCL
[0C8
H
]
WDTR5 WDTR4 WDTR3 WDTR2WDTR1 WDTR0
Watch Dog Timer Operation
0:Free-run
1:Automatically cleared, after one machine cycle
IFBIT
WDTON
To Reset circuit
Clear6
W
W
W
W
W
W
W
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