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參數(shù)資料
| 型號： | HMD16M36M12EG-6 |
| 廠商： | Hanbit Electronics Co.,Ltd. |
| 英文描述： | 64Mbyte (16Mx36) EDO/with Parity Mode 4K Ref. 72pin-SIMM Design |
| 中文描述： | 64Mbyte（16Mx36）江戶/有校驗(yàn)?zāi)Ｊ?K的參考。 72pin，上海藥物研究所設(shè)計(jì) |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 93K |
| 代理商： | HMD16M36M12EG-6 |
HANBit HMD16M36M12EG
URL:www.hbe.co.kr HANBit Electronics Co.,Ltd.
REV.1.0(August.2002)
- 5 -
/RAS to column address delay time
t
RAD
15
25
15
30
ns
/CAS to /RAS precharge time
t
CRP
5
5
ns
Row address set-up time
t
ASR
0
0
ns
Row address hold time
t
RAH
10
10
ns
Column address set-up time
t
ASC
0
0
ns
Column address hold time
t
CAH
8
10
ns
Column address hold referenced to /RAS
t
AR
50
55
ns
Column Address to /RAS lead time
t
RAL
25
30
ns
Read command set-up time
t
RCS
0
0
ns
Read command hold referenced to /CAS
t
RCH
0
0
ns
Read command hold referenced to /RAS
t
RRH
0
0
ns
Write command hold time
t
WCH
10
10
ns
Write command hold referenced to /RAS
t
WCR
50
55
ns
Write command pulse width
t
WP
10
10
ns
Write command to /RAS lead time
t
RWL
13
10
ns
Write command to /CAS lead time
t
CWL
8
10
ns
Data-in set-up time
t
DS
0
0
ns
Data-in hold time
t
DH
8
10
ns
Data-in hold referenced to /RAS
t
DHR
50
55
ns
Refresh period
t
REF
64
64
ns
Write command set-up time
t
WCS
0
0
ns
/CAS setup time (C-B-R refresh)
t
CSR
5
5
ns
/CAS hold time (C-B-R refresh)
t
CHR
10
10
ns
/RAS precharge to /CAS hold time
t
RPC
5
5
ns
Access time from /CAS precharge
t
CPA
28
35
ns
Fast page mode cycle time
t
PC
40
45
ns
/CAS precharge time (Fast page)
t
CP
8
10
ns
/RAS pulse width (Fast page )
t
RASP
50 200K
60 200K
ns
/W to /RAS precharge time(C-B-R refresh)
t
WRP
10
10
ns
/W to /RAS hold time (C-B-R refresh)
t
WRH
10
10
ns
/CAS precharge(C-B-R counter test)
t
CPT
20
30
ns
NOTES
1.
An initial pause of 200
μ
s is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.
V
IH (min)
and V
IL (max)
are reference levels for measuring timing of input signals. Transition times are measured between
V
IH(min)
and V
IL(max)
and are assumed to be 5ns for all inputs.
3.
Measured with a load equivalent to 2TTL loads and 100pF
4.
Operation within the t
RCD(max)
limit insures that t
RAC(max)
can be met. t
RCD(max)
is specified as a reference point only. If t
RCD
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相關(guān)代理商/技術(shù)參數(shù) |
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| HMD16M36M12G | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:64Mbyte (16Mx36) FP/with Parity Mode 4K Ref. 72pin-SIMM Design |
| HMD16M36M12G-5 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:64Mbyte (16Mx36) FP/with Parity Mode 4K Ref. 72pin-SIMM Design |
| HMD16M36M12G-6 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:64Mbyte (16Mx36) FP/with Parity Mode 4K Ref. 72pin-SIMM Design |
| HMD16M64B8A-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The HSD16M64B8A is a 16M x 64 bit Synchronous Dynamic RAM high density memory module. |
| HMD16M64B8A-10L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:The HSD16M64B8A is a 16M x 64 bit Synchronous Dynamic RAM high density memory module. |
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