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參數(shù)資料
| 型號(hào)： | HMC660LC4B |
| 廠商： | HITTITE MICROWAVE CORP |
| 元件分類： | 放大器 |
| 英文描述： | 20 MHz - 4500 MHz RF/MICROWAVE WIDE BAND LOW POWER AMPLIFIER |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, SMT, 24 PIN |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 763K |
| 代理商： | HMC660LC4B |
For price, delivery, and to place orders, please contact Hittite Microwave Corporation:
20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373
Order On-line at www.hittite.com
T
R
A
C
K
-A
N
D
-HOL
D
-
SM
T
6
6 - 3
0.02 - 4.5 GHz WIDEBAND,
3 GS/s TRACK-AND-HOLD AMPLIFIER
v02.1208
HMC660LC4B
Electrical Specifications, (continued)
Parameter
Conditions
Test Level
Min.
Typ.
Max.
Units
Clock Slew Rate
Recommended for best linearity
4
V/ns
Input Impedance
50
Ω
Return Loss
0 - 3 GHz
16
dB
Input Resistance
50
Ω
Analog Outputs (OUTP, OUTN)
Differential Full Scale Range
1Vpp
Common Mode Output Voltage
4.0
V
Output Impedance
50
Ω
Return Loss
0 - 4 GHz
15
dB
Track Mode Dynamics
Gain
0dB
Track Mode Bandwidth
@ 1 Vpp Input
3.95
GHz
Lower Frequency Corner
16
MHz
Single Tone SFDR @ 500 MHz
1 Vpp Input
54.8
dB
Single Tone SFDR @ 1000 MHz
1 Vpp Input
54.7
dB
Single Tone SFDR @ 2000 MHz
1 Vpp Input
52.6
dB
Single Tone SFDR @ 3000 MHz
1 Vpp Input
50.4
dB
Single Tone SFDR @ 4000 MHz
1 Vpp Input
49
dB
Two Tone SFDR @ 500 MHz
0.5 Vpp Input
57.4
dB
Two Tone SFDR @ 995/1005 MHz
0.5 Vpp Input per Tone
56.4
dB
Two Tone SFDR @ 1995/2005 MHz
0.5 Vpp Input per Tone
54.5
dB
Two Tone SFDR @ 2995/3005 MHz
0.5 Vpp Input per Tone
52.5
dB
Two Tone SFDR @ 3995/4005 MHz
0.5 Vpp Input per Tone
50.2
dB
Noise Spectral Density
@ 1 GHz
8.9
nV/√Hz
Integrated Noise [2]
0.95
mV RMS
Hold Mode Dynamics
Sampling Bandwidth
@ -3 dB Gain, 1 Vpp Input Level
4.5
GHz
Differential Droop Rate
0.5
%/ns
Feedthrough Rejection
0 - 4000 MHz
≥ 60
dB
Integrated Noise [2]
500 MHz Clock Frequency
1.04
mV RMS
Maximum Hold Time
5ns
Single Tone THD/SFDR 995 MHz
[1]
-54 / 54
dB
Single Tone THD/SFDR 1995 MHz
[1]
-58 / 58
dB
Single Tone THD/SFDR 2995 MHz
[1]
-59 / 61
dB
Single Tone THD/SFDR 3995 MHz
[1]
-54 / 54
dB
Track-to-Hold Switching
Aperture Delay
-6
ps
Aperture Jitter
[1]
84
fs
Settling Time to 1 mV
Simulated Value
206
ps
Differential Pedestal
500 MHz Clock Frequency,
0 dBm Clock Power
-0.3
%
Clock Frequency
100
3000
MHz
Clock Buffer Pipeline Delay
38
ps
[1] 1 Vpp Input Level, 1 GS/s Clock, Clock Power = 6 dBm / input terminal.
[2] Noise bandwidth limited by output amplifier bandwidth of ~7 GHz.
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