參數(shù)資料
型號: HMC492LP3
廠商: 美國訊泰微波有限公司上海代表處
元件分類: FPGA
英文描述: 800000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述: 貼片砷化鎵HBT MMIC的分頻2,區(qū)- 18吉赫
文件頁數(shù): 1/6頁
文件大?。?/td> 256K
代理商: HMC492LP3
MICROWAVE CORPORATION
10 - 118
For price, delivery, and to place orders, please contact Hittite Microwave Corporation:
12 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373
Order Online at www.hittite.com
F
10
HMC492LP3
SMT GaAs HBT MMIC
DIVIDE-BY-2, DC - 18 GHz
General Description
Features
Functional Diagram
The HMC492LP3 is a low noise Divide-by-2
Static Divider utilizing InGaP GaAs HBT technol-
ogy packaged in a leadless 3x3 mm QFN surface
mount plastic package. This device operates from
DC (with a square wave input) to 18 GHz input
frequency from a single +5.0V DC supply. The
low additive SSB phase noise of -150 dBc/Hz at
100 kHz offset helps the user maintain excellent
system noise performance.
Ultra Low SSB Phase Noise: -150 dBc/Hz
Very Wide Bandwidth
Output Power: -4 dBm
Single DC Supply: +5V
3 x 3 x 1 mm QFN SMT Package
Typical Applications
Prescaler for DC to 18 GHz PLL Applications:
Point-to-Point / Multi-Point Radios
VSAT Radios
Fiber Optic
Test Equipment
Military
Electrical Specifications,
T
A
= +25° C, 50 Ohm System, Vcc= +5V
1. Divider will operate down to DC for square-wave input signal.
v01.0604
Parameter
Conditions
Min.
Typ.
Max.
Units
Maximum Input Frequency
18
19
GHz
Minimum Input Frequency
Sine Wave Input. [1]
0.2
0.5
GHz
Input Power Range
Fin = 2 to 14 GHz
-15
-20
+10
dBm
Fin = 14 to 16 GHz
-15
-20
+5
dBm
Fin = 16 to 18 GHz
-10
-15
0
dBm
Output Power
Fin = 0.5 to 18 GHz
-7
-4
dBm
Reverse Leakage
Both RF Outputs Terminated
60
dB
SSB Phase Noise (100 kHz offset)
Pin = 0 dBm, Fin = 4.8 GHz
-150
dBc/Hz
Output Transition Time
Pin = 0 dBm, Fout = 882 MHz
100
ps
Supply Current (Icc1 + Icc2)
78
mA
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