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參數(shù)資料
| 型號(hào)： | HMA510883 |
| 廠商： | Intersil Corporation |
| 英文描述： | Multilayer Ferrite Bead; Impedance:70ohm; Current Rating:0.6A; Terminal Type:PCB Surface Mount; Inductance:70uH; Leaded Process Compatible:Yes; Mounting Type:Surface Mount; Package/Case:1206; Packaging:Cut Tape |
| 中文描述： | 16 × 16位并行乘加器的CMOS |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大小： | 180K |
| 代理商： | HMA510883 |
3-12
SUB
I
Subtract Control. When both SUB and ACC are HIGH, the Accumulator Register contents are sub-
tracted from the current product. When ACC is HIGH and SUB is LOW, the Accumulator Register
contents and the current product are summed. The SUB control input is latched on the rising edge of
CLKX or CLKY.
RND
I
Round Control. When this control is HIGH, a one is added to the most significant bit of the LSP. When
LOW, the product is unchanged.
PREL
I
Preload Control. When this control is HIGH, the three bidirectional ports may be used to preload the
Accumulator Registers. The three-state controls (OEX, OEM, OEL) must be HIGH, and the data will
be preloaded on the rising edge of CLKP. When this control is LOW, the Accumulator Registers func-
tion in a normal manner.
OEL
I
Y-Input/LSP Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high
impedance state. This state is required for Y-data input or preloading the LSP Register. When OEL
is LOW, the port is enabled for LSP output.
OEM
I
MSP Output Port Three-State Control. A LOW on this control line enables the port for output. When
OEM is HIGH, the output drivers are in the high impedance state.
This control must be HIGH for preloading the MSP Register.
OEX
I
XTP Output Port Three-State Control. A LOW on this control line enables the port for output. When
OEX is HIGH, the output drivers are in the high impedance state. This control must be HIGH for pre-
loading the XTP Register.
CLKX
I
X-Register Clock. The rising edge of this clock latches the X-Data Input Register along with the TC,
ACC, SUB and RND inputs.
CLKY
I
Y-Register Clock. The rising edge of this clock latches the Y-Data Input Register along with the TC,
ACC, SUB and RND inputs.
CLKP
I
Product Register Clock. The rising edge of CLKP latches the LSP, MSP and XTP Registers. If the
preload control is active, the data on the I/O ports is loaded into these registers. If preload is not ac-
tive, the accumulated product is loaded into the registers.
Pin Descriptions
(Continued)
NAME
TYPE
DESCRIPTION
HMA510/883
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| HMA510GC-55 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:16 x 16-Bit CMOS Parallel Multiplier Accumulator |
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| HMA510GM-65883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:16 x 16-Bit CMOS Parallel Multiplier Accumulator |
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