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參數(shù)資料
| 型號(hào)： | HM9264BLP-8L |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 64 k SRAM (8-kword x 8-bit) |
| 中文描述： | 64畝的SRAM（8 - KWord的× 8位） |
| 文件頁(yè)數(shù)： | 6/14頁(yè) |
| 文件大?。?/td> | 73K |
| 代理商： | HM9264BLP-8L |
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HM9264B Series
AC Characteristics
(Ta = 0 to +70
°
C, V
CC
= 5 V
±
10%, unless otherwise noted.)
Test Conditions
Input pulse levels: 0.8 V to 2.4 V
Input and output timing reference level: 1.5 V
Input rise and fall time: 10 ns
Output load: 1 TTL Gate + C
L
(100 pF) (Including scope & jig)
Read Cycle
HM9264B-8L
HM9264B-10L
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
CO1
t
CO2
t
OE
t
LZ1
t
LZ2
t
OLZ
t
HZ1
t
HZ2
t
OHZ
t
OH
85
—
100
—
ns
Address access time
—
85
—
100
ns
Chip select access time
CS1
—
85
—
100
ns
CS2
—
85
—
100
ns
Output enable to output valid
—
45
—
50
ns
Chip selection to output in low-Z
CS1
10
—
10
—
ns
2
CS2
10
—
10
—
ns
2
Output enable to output in low-Z
Chip deselection in to output in high-Z
CS1
5
—
5
—
ns
2
0
30
0
35
ns
1, 2
CS2
0
30
0
35
ns
1, 2
Output disable to output in high-Z
0
30
0
35
ns
1, 2
Output hold from address change
Notes: 1. t
is defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. At any given temperature and voltage condition, t
HZ
maximum is less than t
LZ
minimum both for
a given device and from device to device.
3. Address must be valid prior to or simultaneously with
CS1
going low or CS2 going high.
10
—
10
—
ns
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