參數(shù)資料
型號: HM9264BLP-10L
廠商: Hitachi,Ltd.
英文描述: 64 k SRAM (8-kword x 8-bit)
中文描述: 64畝的SRAM(8 - KWord的× 8位)
文件頁數(shù): 12/14頁
文件大?。?/td> 73K
代理商: HM9264BLP-10L
HM9264B Series
Low V
CC
Data Retention Characteristics
(Ta = 0 to +70
°
C)
Parameter
Symbol
Min
Typ
*1
Max
Unit
Test conditions
*4
CS1
V
CC
–0.2 V,
CS2
V
CC
–0.2 V or CS2
0.2 V
V
= 3.0 V, 0 V
Vin
V
CC
CS1
V
–0.2 V, CS2
V
CC
–0.2 V
or 0 V
CS2
0.2 V
V
CC
for data retention
V
DR
2.0
V
Data retention current
I
CCDR
1
*1
25
*2
μ
A
Chip deselect to data
retention time
t
CDR
0
ns
See retention waveform
Operation recovery time
Notes: 1. Reference data at Ta = 25
°
C.
2. 10
μ
A max at Ta = 0 to + 40
°
C.
3. t
RC
= read cycle time.
4. CS2 controls address buffer,
WE
buffer,
CS1
buffer,
OE
buffer, and Din buffer. If CS2 controls
data retention mode, Vin levels (address,
WE
,
OE
,
CS1
, I/O) can be in the high impedance
state. If
CS1
controls data retention mode, CS2 must be CS2
V
– 0.2 V or 0 V
CS2
0.2
V. The other input levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
t
R
t
RC
*3
ns
Low V
CC
Data Retention Timing Waveform (1)
(
CS1
Controlled)
t
CDR
t
R
Data retention mode
CS1
V
CC
– 0.2 V
V
CC
4.5 V
2.2 V
V
DR
0 V
CS1
Low V
CC
Data Retention Timing Waveform (2)
(CS2 Controlled)
Data retention mode
t
R
t
CDR
CS2
0.2 V
V
CC
4.5 V
V
DR
0 V
CS2
0.4 V
相關(guān)PDF資料
PDF描述
HM9264B 64 k SRAM (8-kword x 8-bit)
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HM9264BLFP-10L 64 k SRAM (8-kword x 8-bit)
HM9264BLFP-8L 64 k SRAM (8-kword x 8-bit)
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