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參數(shù)資料
| 型號： | HM67S18258 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4M Synchronous Fast Static RAM (256k-words ×18-bits)(4M 同步快速靜態(tài)RAM (256k字 ×18位)) |
| 中文描述： | 4分同步快速靜態(tài)存儲器（256k -字× 18位）（4分同步快速靜態(tài)隨機存儲器（256k字× 18位）） |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 184K |
| 代理商： | HM67S18258 |
HM67S18258 Series
20
Boundary Scan Order
Bit #
Bump ID
Signal Name
Bit #
Bump ID
Signal Name
1
5R
M2
27
2B
NC
2
6T
SA4
28
3A
SA14
3
4P
SA5
29
3C
SA15
4
6R
SA6
30
2C
SA16
5
5T
SA7
31
2A
SA17
6
7T
ZZ
32
1D
DQc0
7
7P
DQa0
33
2E
DQc1
8
6N
DQa1
34
2G
DQc2
9
6L
DQa2
35
1H
DQc3
SWEc
10
7K
DQa3
SWEa
K
36
3G
11
5L
37
4D
NC
SS
12
4L
38
4E
13
4K
K
G
39
4G
NC
14
4F
40
4H
NC
SWE
15
6H
DQa4
41
4M
16
7G
DQa5
42
2K
DQc4
17
6F
DQa6
43
1L
DQc5
18
7E
DQa7
44
2M
DQc6
19
6D
DQa8
45
1N
DQc7
20
6A
SA8
46
2P
DQc8
21
6C
SA9
47
3T
SA0
22
5C
SA10
48
2R
SA1
23
5A
SA11
49
4N
SA2
24
6B
NC
50
2T
SA3
25
5B
SA12
51
3R
M1
26
Notes: 1. Bit#1 is the first scan bit to exit the chip.
2. NC pads listed in the TABLE are represented in the Boundary Scan Register by a Place Holder.
Place Holder registers are internally connected to V
SS
.
3. The clock pins (K and
K
) are needed as PECL differential levels. And, clock reciever generated
single clock signal. This signal and its inverted signal are used for Boundary Scan Register input
signal.
3B
SA13
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相關(guān)代理商/技術(shù)參數(shù) |
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| HM67S18258BP-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 Fast Synchronous SRAM |
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| HM67S222LFTR13 | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Surface Mount Common Mode Chokes |
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| HM67-S250LF | 制造商:BITECH 制造商全稱:Bi technologies 功能描述:Surface Mount Common Mode Chokes |
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