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參數(shù)資料
| 型號： | HM658512ALTT-7V |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | FPGA |
| 英文描述： | 50000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 4個M移動存儲芯片（512 KWord的× 8位）2度刷新 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 105K |
| 代理商： | HM658512ALTT-7V |
HM658512A Series
7
At the end of self refresh, refresh reset time (t
RFS
) is required to reset the internal self refresh operation of
the RAM. During t
,
CE
and
OE
/
RFSH
must be kept high. If auto refresh follows self refresh, low
transition of
OE
/
RFSH
at the beginning of automatic refresh must not occur during t
RFS
period.
Notes on Using the HM658512A
Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive
than conventional SRAM’s.
(1) If a short
CE
pulse of a width less than t
CE
min is applied to RAM, an incomplete read occurs and
stored data may be destroyed. Make sure that
CE
low pulses of less than t
CE
min are inhibited. Note
that a 10 ns
CE
low pulse may sometimes occur owing to the gate delay on the board if the
CE
signal is
generated by the decoding of higher address signals on the board. Avoid these short pulses.
(2)
OE
/
RFSH
works as refresh control in standby mode. A short
OE
/
RFSH
low pulse may cause an
incomplete refresh that will destroy data. Make sure that
OE
/
RFSH
low pulse of less than t
FAP
min are
also inhibited.
(3) t
OHC
and t
OCD
are the timing specs which distinguish the
OE
function of
OE
/
RFSH
from the
RFSH
function. The t
OHC
and t
OCD
specs must be strictly maintained.
(4) Start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100
μs after the power voltage reaches 4.5 V-5.5 V after power-on.
Function Table
CE
OE
/
RFSH
WE
I/O pin
Mode
L
L
H
Dout
Read
L
X
L
High-Z
Write
L
H
H
High-Z
—
H
L
X
High-Z
Refresh
H
Note:
H
X
High-Z
Standby
X means H or L.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM658512ALTT-8 | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALTT-8V | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALRR-10V | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALRR-7 | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM65W8512 | 4 M PSRAM (512-kword ×8-bit)(4 M PSRAM (512k字 ×8位)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM658512ALTT-8 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALTT-8V | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ASERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| HM658512DFP-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
| HM658512DFP-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
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