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參數(shù)資料
| 型號： | HM658512ALTT-7 |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | FPGA |
| 英文描述： | 50000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 4個M移動存儲芯片（512 KWord的× 8位）2度刷新 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大?。?/td> | 105K |
| 代理商： | HM658512ALTT-7 |
HM658512A Series
11
AC Characteristics
(Ta = 0 to +70°C, V
CC
= 5 V ± 10%, unless otherwise noted.)
(cont.)
HM658512A
-7
-8
-10
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit
Notes
Data in to end of write
t
DW
t
DH
t
OW
t
WHZ
t
T
t
RFD
t
FP
t
FAP
20
—
20
—
25
—
ns
Data in hold time for write
0
—
0
—
0
—
ns
Output active from end of write
5
—
5
—
5
—
ns
2
Write to output in high-Z
—
20
—
20
—
25
ns
1, 2
Transition time (rise and fall)
3
50
3
50
3
50
ns
6
Refresh command delay time
35
—
40
—
50
—
ns
Refresh precharge time
35
—
40
—
40
—
ns
Refresh command pulse width for
automatic refresh
70 n
8
μ
80 n
8
μ
80 n
8
μ
s
Automatic refresh cycle time
t
FC
t
FAS
115
—
130
—
160
—
ns
Refresh command pulse width for
self refresh
8
—
8
—
8
—
μ
s
Refresh reset time from self refresh t
RFS
Refresh period
600
—
600
—
600
—
ns
9
t
REF
—
32
—
32
—
32
ms
2048
cycle
Notes: 1. t
CHZ
, t
OHZ
, t
WHZ
are defined as the time at which the output achieves the open circuit condition.
2. t
CHZ
, t
CLZ
, t
OHZ
, t
OLZ
, t
WHZ
and t
OW
are sampled under the condition of t
T
= 5 ns and not 100% tested.
3. A write occurs during the overlap of low
CE
and low
WE
. Write end is defined at the earlier of
WE
going high or
CE
going high.
4. If the
CE
low transition occurs simultaneously with or from the
WE
low transition, the output
buffers remain in high impedance state.
5. In write cycle,
OE
or
WE
must disable output buffers prior to applying data to the device and at
the end of write cycle data inputs must be floated prior to
OE
or
WE
turning on output buffers.
During this period, I/O pins are in the output state, therefore the input signals of opposite phase
to the outputs must not be applied.
6. Transition time t
is measured between V
(min) and V
IL
(max). V
IH
(min) and V
IL
(max) are
reference levels for measuring timing of input signals.
7. After power-up, pause for more than 100
μ
s and execute at least 8 initialization cycles.
8. 2048 cycles of burst refresh or the first cycle of distributed automatic refresh must be executed
within 15
μ
s after self refresh, in order to meet the refresh specification of 32 ms and 2048
cycles.
9. At the end of self refresh, refresh reset time (t
) is required to reset the internal self refresh
operation of the RAM. During t
,
CE
and
OE
/
RFSH
must be kept high. If automatic refresh
follows self refresh, low transition of
OE
/
RFSH
at the beginning of automatic refresh must not
occur during t
RFS
period.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM658512ALTT-7V | 50000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| HM658512ALTT-8 | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALTT-8V | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALRR-10V | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALRR-7 | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM658512ALTT-7V | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALTT-8 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALTT-8V | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ASERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| HM658512DFP-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Pseudo-Static RAM |
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