- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370637 > HM658512ALP-10V (Hitachi,Ltd.) 50000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN PDF資料下載
參數(shù)資料
| 型號： | HM658512ALP-10V |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | FPGA |
| 英文描述： | 50000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 4個M移動存儲芯片（512 KWord的× 8位）2度刷新 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大小： | 105K |
| 代理商： | HM658512ALP-10V |
HM658512A Series
6
Pin Functions
CE
: Chip Enable (Input)
CE
is a basic clock. RAM is active when
CE
is low, and is on standby when
CE
is high.
A0 to A18: Address Inputs (Input)
A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18
are fetched into RAM by the falling edge of
CE
.
OE
/
RFSH
: Output Enable/Refresh (Input)
This pin has two functions. Basically it works as
OE
when
CE
is low, and as
RFSH
when
CE
is high
(in standby mode). After a read or write cycle finishes, refresh does not start if
CE
goes high while
OE
/
RFSH
is held low. In order to start a refresh in standby mode,
OE
/
RFSH
must go high to reset the
refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when
OE
/
RFSH
goes
low.
I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins.
WE
: Write Enable (Input)
RAM is in write mode when
WE
is low, and is in read mode when
WE
is high. I/O data is fetched into
RAM by the rising edge of
WE
or
CE
(earlier timing) and the data is written into memory cells.
Refresh
There are three refresh modes : address refresh, automatic refresh and self refresh.
(1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one
method of accessing those addresses. Each row address (2048 addresses of A0 to A10)must be read at
least once every 32 ms. In address refresh mode,
OE
/
RFSH
can remain high. In this case, the I/O pins
remain at high impedance, but the refresh is done within RAM.
(2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic
refresh mode if
OE
/
RFSH
falls while
CE
is high and it remains low for at least t
FAP
. One automatic
refresh cycle is executed by one low pulse of
OE
/
RFSH
. It is not necessary to input the refresh
address from outside since it is generated internally by an on-chip address counter. 2048 automatic
refresh cycles must be done every 32 ms.
(3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh
starts automatically when
OE
/
RFSH
stays low for more than 8 μs. Refresh addresses are automatically
specified by the on-chip address counter, and the refresh period is determined by the on-chip timer.
Automatic refresh and self refresh are distinguished from each other by the width of the
OE
/
RFSH
low
pulse in standby mode. If the
OE
/
RFSH
low pulse is wider than 8 μs, RAM becomes into self refresh
mode; if the
OE
/
RFSH
low pulse is less than 8 μs, it is recognized as an automatic refresh instruction.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM658512ALP-7 | 50000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| HM658512ALP-7V | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALP-8 | 4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALP-8V | 50000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| HM658512ALRR-7V | 50000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM658512ALP-7 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALP-7V | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALP-8 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
| HM658512ALP-85V | 制造商:HITCHI 功能描述: |
| HM658512ALP-8V | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:4 M PSRAM (512-kword x 8-bit) 2 k Refresh |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。