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參數(shù)資料
| 型號： | HM62W16255HLTT-12 |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | SRAM |
| 英文描述： | 4M High Speed SRAM (256-kword x 16-bit) |
| 中文描述： | 4分高速SRAM（256 - KWord的x 16位） |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 101K |
| 代理商： | HM62W16255HLTT-12 |
HM62W16255H Series
7
AC Characteristics
(Ta = 0 to +70
°
C, V
CC
= 3.3 V
±
0.3 V, unless otherwise noted.)
Test Conditions
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
Output load (B)
(for t
CLZ
, t
OLZ
, t
LBLZ
, t
UBLZ
, t
CHZ
, t
OHZ
,
t
LBHZ
, t
UBHZ
, t
WHZ
, and t
OW
)
Dout
353
319
3.3 V
5 pF
Dout
RL=50
Output load (A)
1.5 V
Zo=50
Read Cycle
HM62W16255H
-12
-15
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
ACS
t
OE
t
LB
, t
UB
t
OH
t
CLZ
t
OLZ
t
LBLZ
, t
UBLZ
t
CHZ
t
OHZ
t
LBHZ
, t
UBHZ
12
—
15
—
ns
Address access time
—
12
—
15
ns
Chip select access time
—
12
—
15
ns
Output enable to output valid
—
6
—
7
ns
Byte select to output valid
—
6
—
7
ns
Output hold from address change
3
—
3
—
ns
Chip select to output in low-Z
3
—
3
—
ns
1
Output enable to output in low-Z
0
—
0
—
ns
1
Byte select to output in low-Z
0
—
0
—
ns
1
Chip deselect to output in high-Z
—
6
—
7
ns
1
Output disable to output in high-Z
—
6
—
7
ns
1
Byte deselect to output in high-Z
—
6
—
7
ns
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM62W16255HLTT-15 | 4M High Speed SRAM (256-kword x 16-bit) |
| HM62W16255HJP-15 | 4M High Speed SRAM (256-kword x 16-bit) |
| HM62W16255HLJP-12 | 4M High Speed SRAM (256-kword x 16-bit) |
| HM62W16255HLJP-15 | 4M High Speed SRAM (256-kword x 16-bit) |
| HM62W16255HTT-12 | 4M High Speed SRAM (256-kword x 16-bit) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM62W4100HJP15 | 制造商:Renesas Electronics Corporation 功能描述: |
| HM62W8512BLFP-5 | 制造商:HITACHI 功能描述: |
| HM62W8512BLTTI7 | 制造商:Hitachi 功能描述: |
| HM-630 | 制造商:Black Box Corporation 功能描述:FACE PLATE:HM-STAINLESS |
| HM63021FP | 制造商:Panasonic Industrial Company 功能描述:IC |
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