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參數(shù)資料
| 型號(hào)： | HM62W16255HI |
| 廠商： | Hitachi,Ltd. |
| 元件分類： | SRAM |
| 英文描述： | 4M High Speed SRAM (256-kword x 16-bit) |
| 中文描述： | 4分高速SRAM（256 - KWord的x 16位） |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 92K |
| 代理商： | HM62W16255HI |
HM62W16255HC Series
8
AC Characteristics
(Ta = 0 to +70
°
C, V
CC
= 3.3 V
±
0.3 V, unless otherwise noted.)
Test Conditions
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
Output load (B)
(for t
CLZ
, t
OLZ
, t
LBLZ
, t
UBLZ
, t
CHZ
, t
OHZ
,
t
LBHZ
, t
UBHZ
, t
WHZ
, and t
OW
)
Dout
353
319
3.3 V
5 pF
1.5 V
30 pF
Dout
RL=50
Output load (A)
Zo=50
Read Cycle
HM62W16255HC
-10
Parameter
Symbol
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
ACS
t
OE
t
LB
, t
UB
t
OH
t
CLZ
t
OLZ
t
LBLZ
, t
UBLZ
t
CHZ
t
OHZ
t
LBHZ
, t
UBHZ
10
—
ns
Address access time
—
10
ns
Chip select access time
—
10
ns
Output enable to output valid
—
5
ns
Byte select to output valid
—
5
ns
Output hold from address change
3
—
ns
Chip select to output in low-Z
3
—
ns
1
Output enable to output in low-Z
0
—
ns
1
Byte select to output in low-Z
0
—
ns
1
Chip deselect to output in high-Z
—
5
ns
1
Output disable to output in high-Z
—
5
ns
1
Byte deselect to output in high-Z
—
5
ns
1
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| HM62W16255HC | 4M High Speed SRAM (256-kword x 16-bit) |
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