參數(shù)資料
型號(hào)： HM62V8100I
廠商： Renesas Technology Corp.
英文描述： Wide Temperature Range Version 8 M SRAM (1024-kword ?8-bit)
中文描述： 寬溫版本八米的SRAM（1024 - KWord的？8位）
文件頁(yè)數(shù)： 17/21頁(yè)
文件大?。?/td> 110K
代理商： HM62V8100I
HM62V8100I Series
15
Low V
CC
Data Retention Characteristics
(Ta = –40 to +85
°
C)
Parameter
Symbol
Min
Typ
*
4
Max
Unit
Test conditions
*
3
V
CC
for data retention
V
DR
2.0
—
3.6
V
Vin
≥
0V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
– 0.2 V
CS1
≥
V
CC
– 0.2 V
V
= 3.0 V, Vin
≥
0V
(1) 0 V
≤
CS2
≤
0.2 V or
(2) CS2
≥
V
CC
– 0.2 V,
CS1
≥
V
CC
– 0.2 V
Data retention current
I
CCDR
*
1
—
0.5
25
μ
A
I
CCDR
*
2
t
CDR
—
0.5
10
μ
A
Chip deselect to data
retention time
0
—
—
ns
See retention waveform
Operation recovery time
Notes: 1. This characteristic is guaranteed only for L version.
2. This characteristic is guaranteed only for L-SL version.
3. CS2 controls address buffer,
WE
buffer,
CS1
buffer,
OE
buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address,
WE
,
OE
,
CS1
, I/O) can be in the high impedance state. If
CS1
controls data retention mode, CS2 must be CS2
≥
V
– 0.2 V or 0 V
≤
CS2
≤
0.2 V. The other
input levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
4. Typical values are at V
CC
= 3.0 V, Ta = +25C and not guaranteed.
5. t
RC
= read cycle time.
t
R
t
RC
*
5
—
—
ns
相關(guān)PDF資料
PDF描述
HM62V8100LBPI-5 Wide Temperature Range Version 8 M SRAM (1024-kword ?8-bit)
HM62V8100LBPI-5SL Wide Temperature Range Version 8 M SRAM (1024-kword ?8-bit)
HM62V8100LTTI-5 Wide Temperature Range Version 8 M SRAM (1024-kword ?8-bit)
HM62V8100LTTI-5SL Wide Temperature Range Version 8 M SRAM (1024-kword ?8-bit)
HM62V8100L Wide Temperature Range Version 8 M SRAM (1024-kword x 8-bit)
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