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參數(shù)資料
| 型號： | HM62V16256BLTT-7 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 4 M SRAM (256-kword x 16-bit) |
| 中文描述： | 四米的SRAM（256 - KWord的x 16位） |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 78K |
| 代理商： | HM62V16256BLTT-7 |
HM62V16256B Series
8
Write Cycle
HM62V16256B
-7
-8
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
t
AW
t
CW
t
WP
t
BW
t
AS
t
WR
t
DW
t
DH
t
OW
70
—
85
—
ns
Address valid to end of write
60
—
70
—
ns
Chip selection to end of write
60
—
70
—
ns
5
Write pulse width
LB
,
UB
valid to end of write
50
—
55
—
ns
4
55
—
70
—
ns
Address setup time
0
—
0
—
ns
6
Write recovery time
0
—
0
—
ns
7
Data to write time overlap
30
—
35
—
ns
Data hold from write time
0
—
0
—
ns
Output active from end of write
5
—
5
—
ns
2
Output disable to output in High-Z t
OHZ
Write to output in high-Z
Notes: 1. t
, t
, t
and t
are defined as the time at which the outputs achieve the open circuit
conditions and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, t
HZ
max is less than t
LZ
min both for a given device
and from device to device.
4. A write occures during the overlap of a low
CS1
, a high CS2, a low
WE
and a low
LB
or a low
UB
.
A write begins at the latest transition among
CS1
going low, CS2 going high,
WE
going low and
LB
going low or
UB
going low. A write ends at the earliest transition among
CS1
going high, CS2
going low,
WE
going high and
LB
going high or
UB
going high. t
WP
is measured from the beginning
of write to the end of write.
5. t
CW
is measured from the later of
CS1
going low or CS2 going high to the end of write.
6. t
AS
is measured from the address valid to the beginning of write.
7. t
is measured from the earliest of
CS1
or
WE
going high or CS2 going low to the end of write
cycle.
0
25
0
25
ns
1, 2
t
WHZ
0
25
0
25
ns
1, 2
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|---|---|
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