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參數(shù)資料
| 型號： | HM62V16100LTI-5SL |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Wide Temperature Range Version |
| 中文描述： | 寬溫版本 |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 215K |
| 代理商： | HM62V16100LTI-5SL |
HM62V16100I Series
Rev.2.00, Oct.06.2003, page 13 of 23
Read Cycle
HM62V16100I
-4
-5
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read cycle time
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
OH
t
BA
t
CLZ1
t
CLZ2
t
BLZ
t
OLZ
t
CHZ1
t
CHZ2
t
BHZ
t
OHZ
45
10
10
45
55
10
10
55
ns
Address access time
ns
Chip select access time
45
55
ns
45
55
ns
Output enable to output valid
Output hold from address change
LB
,
UB
access time
30
45
20
35
55
20
ns
ns
ns
Chip select to output in low-Z
ns
2, 3
LB
,
UB
enable to low-Z
10
10
ns
2, 3
5
5
ns
2, 3
Output enable to output in low-Z
5
5
ns
2, 3
Chip deselect to output in high-Z
0
0
ns
1, 2, 3
LB
,
UB
disable to high-Z
0
20
0
20
ns
1, 2, 3
0
15
0
20
ns
1, 2, 3
Output disable to output in high-Z
0
15
0
20
ns
1, 2, 3
Write Cycle
HM62V16100I
-4
-5
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
t
AW
t
CW
t
WP
t
BW
t
AS
t
WR
t
DW
t
DH
t
OW
t
OHZ
t
WHZ
45
15
55
20
ns
Address valid to end of write
45
50
ns
Chip selection to end of write
45
50
ns
5
Write pulse width
LB
,
UB
valid to end of write
35
40
ns
4
45
50
ns
Address setup time
0
0
ns
6
Write recovery time
0
0
ns
7
Data to write time overlap
25
25
ns
Data hold from write time
0
0
ns
Output active from end of write
5
5
ns
2
Output disable to output in high-Z
0
0
ns
1, 2
Write to output in high-Z
0
15
0
20
ns
1, 2
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