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參數(shù)資料
| 型號： | HM62G36256BP-4 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8M Synchronous Fast Static RAM(256k-word x 36-bit) |
| 中文描述： | 分同步快速靜態(tài)存儲(chǔ)器（256k字× 36位） |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 137K |
| 代理商： | HM62G36256BP-4 |
HM62G36256 Series
16
Boundary Scan Test Access Port Operations
In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary
scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 -
1990. But does not implement all of the functions required for 1149.1 compliance The HM62Gxx series
contains a TAP controller. Instruction register, Boundary scans register, Bypass register and ID register.
Test Access Port Pins
Symbol I/O
Name
TCK
Test clock
TMS
Test mode select
TDI
Test data in
TDO
Note:
Test data out
This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1.
To disable the TAP, TCK must be connected to V
SS
. TDO should be left unconnected.
To test Boundary scan, ZZ pin need to be kept below V
REF
– 0.4 V.
TAP DC Operating Conditions
(Ta = 0 to 70
°
C, [Tj max = 110
°
C])
Parameter
Symbol
Min
Max
Unit
Notes
Boundary scan input high voltage
V
IH
V
IL
I
LI
V
OL
V
OH
2.0
V
DD
+ 0.3
0.8
V
Boundary scan input low voltage
–0.5
V
Boundary scan input leakage current
–2
2
μ
A
1
Boundary scan output low voltage
—
0.4
V
2
Boundary scan output high voltage
Notes: 1. 0
≤
Vin
≤
V
DD
for all logic input pin.
2. I
OL
= 8 mA.
3. I
OH
= –8 mA.
2.4
—
V
3
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