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參數(shù)資料
| 型號(hào)： | HM62G18512BP-5 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8M Synchronous Fast Static RAM(512k-word x 18-bit) |
| 中文描述： | 分同步快速靜態(tài)存儲(chǔ)器（為512k字× 18位） |
| 文件頁數(shù)： | 3/23頁 |
| 文件大?。?/td> | 121K |
| 代理商： | HM62G18512BP-5 |
HM62G18512 Series
3
Pin Description
Name
I/O type
Descriptions
Notes
V
DD
V
SS
V
DDQ
V
REF
K
K
SS
SWE
Supply
Core power supply
Supply
Ground
Supply
Output power supply
Supply
Input reference: provides input reference voltage
Input
Clock input. Active high.
Input
Clock input. Active low.
Input
Synchronous chip select
Input
Synchronous write enable
SAn
SWEx
G
Input
Synchronous address input
n = 0, 1, 2...18
Input
Synchronous byte write enables
x = a, b
Input
Asynchronous output enable
ZZ
Input
Power down mode select
ZQ
Input
Output impedance control
1
DQxn
I/O
Synchronous data input/output
x = a, b
n = 0, 1, 2...8
M1, M2
Input
Output protocol mode select
TMS
Input
Boundary scan test mode select
TCK
Input
Boundary scan test clock
TDI
Input
Boundary scan test data input
TDO
Output
Boundary scan test data output
NC
—
No connection
M1
M2
Protocol
Notes
V
SS
Notes: 1. ZQ is to be connected to V
via a resistance RQ where 150
≤
RQ
≤
300
, if ZQ = V
or
open, output buffer impedance will be maximum. A case of minimum impedance, it needs to
connect over 120
between ZQ and V
SS
.
2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either V
or V
SS
respectively. The state of the Mode control inputs must be set before power-up and must not
change during device operation. Mode control inputs are not standard inputs and may not meet
V
or V
specification. This SRAM is tested only in the synchronous register to register
operation.
V
DD
Synchronous register to register operation
2
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| HM62G18512 | 8M Synchronous Fast Static RAM (512k-word ×18-bit)(8M 同步快速靜態(tài)RAM (512k字 ×18位)) |
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