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參數(shù)資料
| 型號： | HM6264P-15 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 8192-word x 8-bit High Speed CMOS Static RAM |
| 中文描述： | 8192字× 8位高速CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 82K |
| 代理商： | HM6264P-15 |
HM6264B Series
Write Cycle
HM6264B-8L
HM6264B-10L
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write cycle time
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
t
OHZ
85
—
100
—
ns
Chip selection to end of write
75
—
80
—
ns
2
Address setup time
0
—
0
—
ns
3
Address valid to end of write
75
—
80
—
ns
Write pulse width
55
—
60
—
ns
1, 6
Write recovery time
WE
to output in high-Z
0
—
0
—
ns
4
0
30
0
35
ns
5
Data to write time overlap
40
—
40
—
ns
Data hold from write time
0
—
0
—
ns
Output active from end of write
5
—
5
—
ns
Output disable to output in high-Z
Notes: 1. A write occurs during the overlap of a low
CS1
, and high CS2, and a high
WE
. A write begins
at the latest transition among
CS1
going low,CS2 going high and
WE
going low. A write ends
at the earliest transition among
CS1
going high CS2 going low and
WE
going high. Time t
WP
is
measured from the beginning of write to the end of write.
2. t
CW
is measured from the later of
CS1
going low or CS2 going high to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
is measured from the earliest of
CS1
or
WE
going high or CS2 going low to the end of write
cycle.
5. During this period, I/O pins are in the output state, therefore the input signals of the opposite
phase to the outputs must not be applied.
6. In the write cycle with
OE
low fixed, t
WP
must satisfy the following equation to avoid a problem
of data bus contention
t
WP
≥
t
WHZ
max + t
DW
min.
0
30
0
35
ns
5
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