參數(shù)資料
型號: HM6264ALP-15L
廠商: Hitachi,Ltd.
英文描述: 3-Line To 8-Line Decoders/Demultiplexers 16-CFP -55 to 125
中文描述: 8192字× 8位高速CMOS靜態(tài)RAM
文件頁數(shù): 9/10頁
文件大?。?/td> 54K
代理商: HM6264ALP-15L
9
HM6264A Series
HM6264A Series
Low V
CC
Data Retention
Low VCCData Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only L/LL-version.
Parameter
Symbol
Min
Typ
Max
Unit
Test Condition
V
CC
for data retention
V
DR
2.0
V
CS1
V
CC
– 0.2 V,
CS2
V
CC
– 0.2 V, or
CS2
0.2 V
Data retention current
I
CCDR
1
*1
50
*1
μA
V
CC
= 3.0 V,
CS1
V
CC
– 0.2 V,
CS2
V
CC
– 0.2 V, or
0 V
CS2
0.2 V, 0 V
Vin
1
*2
25
*2
Chip deselect to data
retention time
t
CDR
0
ns
See retention waveform
Operation recovery time
t
R
t
RC*3
ns
See retention waveform
Notes:
1. V
IL
min = –0.3 V, 20 μA max at Ta = 0 to 40°C. These characteristics are guaranteed only for
the L-version.
2. V
IL
min = –0.3 V, 10 μA max at Ta = 0 to 40°C. These characteristics are guaranteed only for
the LL-version.
3. t
RC
= Read cycle time.
Low V
CC
Data Retention Waveform (1)
(
CS1
Controlled)
In data retention mode, CS2 controls the address,
WE
,
CS1
,
OE
, and the Din buffer. If CS2 controls
data retention mode, Vin (for these inputs) can be
in the high impedance state. If CS1 controls the
data retention mode, CS2 must satisfy either
CS2
V
CC
– 0.2 V or CS2
0.2 V. The other
input levels (address,
WE
,
OE
, I/O) can be in the
high impedance state.
t
CDR
t
R
Data retention mode
CS1
V
CC
– 0.2 V
V
CC
4.5 V
2.2 V
V
DR
0 V
CS1
相關(guān)PDF資料
PDF描述
HM6264ALP-15LT 3-Line To 8-Line Decoders/Demultiplexers 16-CDIP -55 to 125
HM6264ALP-15T 3-Line To 8-Line Decoders/Demultiplexers 16-CFP -55 to 125
HM6264ALSP-10 3-Line To 8-Line Decoders/Demultiplexers 16-CDIP -55 to 125
HM6264 64 k SRAM (8-kword x 8-bit)
HM6264A 8192-word x 8-bit High Speed CMOS Static RAM
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