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參數(shù)資料
| 型號(hào)： | HM6264ALFP-12 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | Quadruple 2-Input Positive-NAND Schmitt Triggers 20-LCCC -55 to 125 |
| 中文描述： | 8192字× 8位高速CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大小： | 54K |
| 代理商： | HM6264ALFP-12 |
8
HM6264A Series
HM6264A Series
Write Timing Waveform (2)
(
OE
Low Fix)
t
WC
t
AW
t
CW *2
*6
t
CW *2
t
WP *1
t
AS *3
*5
t
WHZ
t
OH
t
OW
*7
*8
t
DH
t
DW
*9
Address
CS1
CS2
Dout
Din
WE
t
WR *4
Valid Data
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
9.
A write occurs during the overlap of a low
CS1
, a high CS2, and a low
WE
. A write begins
at the latest transition among
CS1
going low, CS2 going high and
WE
going low. A write
ends at the earliest transition among
CS1
going high, CS2 going low and
WE
going high.
Time t
WP
is measured from the beginning of write to the end of write.
t
CW
is measured from the later of
CS1
going low or CS2 going high to the end of write.
t
AS
is measured from the address valid to the beginning of write.
t
WR
is measured from the earliest of
CS1
or
WE
going high or CS2 going low to the end
of the write cycle.
During this period, I/O pins are in the output state, therefore the input signals of opposite
phase to the outputs must not be applied.
If
CS1
goes low simultaneously with
WE
going low or after
WE
goes low, the outputs
remain in high impedance state.
Dout is the same phase of the latest written data in this write cycle.
Dout is the read data of the next address.
If
CS1
is low and CS2 is high during this period, I/O pins are in the output state. Input signals
of opposite phase to the outputs must not be applied to I/O pins
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM6264ALFP-12L | Quadruple 2-Input Positive-NAND Schmitt Triggers 14-CDIP -55 to 125 |
| HM6264ALFP-12LT | Quadruple 2-Input Positive-NAND Schmitt Triggers 14-CFP -55 to 125 |
| HM6264ALFP-12T | 8192-word x 8-bit High Speed CMOS Static RAM |
| HM6264ALFP-15 | Replaced by SN54ALS133 : 13-Input Positive-NAND Gates 16-CFP -55 to 125 |
| HM6264ALFP-15L | Replaced by SN54ALS133 : 13-Input Positive-NAND Gates 16-CDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM6264ALFP-12L | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:8192-word x 8-bit High Speed CMOS Static RAM |
| HM6264ALFP-12LT | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:8192-word x 8-bit High Speed CMOS Static RAM |
| HM6264ALFP-12T | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:8192-word x 8-bit High Speed CMOS Static RAM |
| HM6264ALFP-15 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:8192-word x 8-bit High Speed CMOS Static RAM |
| HM6264ALFP-15L | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:8192-word x 8-bit High Speed CMOS Static RAM |
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