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參數(shù)資料
| 型號： | HM62256LFPI10T |
| 英文描述： | x8 SRAM |
| 中文描述： | x8的SRAM |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 143K |
| 代理商： | HM62256LFPI10T |
HM62256B Series
10
Write Cycle
HM62256B
-4
-5
-7
-8
Parameter
Symbol
Min
Max Min
Max Min
Max Min
Max Unit Notes
Write cycle time
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
45
—
55
—
70
—
85
—
ns
Chip selection to end of write
35
—
40
—
60
—
75
—
ns
4
Address setup time
0
—
0
—
0
—
0
—
ns
5
Address valid to end of write
35
—
40
—
60
—
75
—
ns
Write pulse width
30
—
35
—
50
—
55
—
ns
3, 8
Write recovery time
WE
to output in high-Z
0
—
0
—
0
—
0
—
ns
6
0
20
0
20
0
25
0
40
ns
1, 2, 7
Data to write time overlap
20
—
25
—
30
—
35
—
ns
Data hold from write time
0
—
0
—
0
—
0
—
ns
Output active from end of write
5
—
5
—
5
—
5
—
ns
2
Output disable to output in high-Z t
OHZ
Notes: 1. t
and t
are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (t
) of a low
CS
and a low
WE
. A write begins at the later
transition of
CS
going low or
WE
going low. A write ends at the earlier transition of
CS
going
high or
WE
going high. t
WP
is measured from the beginning of write to the end of write.
4. t
CW
is measured from
CS
going low to the end of write.
5. t
AS
is measured from the address valid to the beginning of write.
6. t
WR
is measured from the earlier of
WE
or
CS
going high to the end of write cycle.
7. Durng this period, I/O pins are in the output state so that the input signals of the opposite
phase to the outputs must not be applied.
8. In the write cycle with
OE
low fixed, t
must satisfy the following equation to avoid a problem
of data bus contention, t
WP
≥
t
WHZ
max + t
DW
min.
0
20
0
20
0
25
0
40
ns
1, 2, 7
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HM62256LFPI12T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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| HM62256LP12 | 制造商:Panasonic Industrial Company 功能描述:IC |
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