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參數(shù)資料
| 型號： | HM62256BLPI-10 |
| 英文描述： | x8 SRAM |
| 中文描述： | x8的SRAM |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 143K |
| 代理商： | HM62256BLPI-10 |
HM62256B Series
13
Low V
CC
Data Retention Characteristics
(Ta = 0 to +70
°
C)
Parameter
Symbol
Min
Typ*
1
Max
Unit
Test Conditions
*6
CS
≥
V
CC
–
0.2 V,
Vin
≥
0 V
V
CC
= 3.0 V, Vin
≥
0 V
CS
≥
V
CC
–
0.2 V,
V
CC
for data retention
V
DR
2.0
—
5.5
V
Data retention current
I
CCDR
—
0.05
30
*2
μ
A
—
0.05
10
*3
—
0.05
3
*4
Chip deselect to data retention time t
CDR
Operation recovery time
Notes: 1. Typical values are at V
CC
= 3.0 V, Ta = 25
°
C and not guaranteed.
2. 10
μ
A max at Ta = 0 to + 40
°
C.
3. This characteristics guaranteed for only L-SL version. 3
μ
A max at Ta = 0 to +40
°
C.
4. This characteristics guaranteed for only L-UL version. 0.6
μ
A max at Ta = 0 to +40
°
C.
5. t
RC
= read cycle time.
6.
CS
controls address buffer,
WE
buffer,
OE
buffer, and Din buffer. If
CS
controls data
retention
mode, other input levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
0
—
—
ns
See retention waveform
t
R
t
RC
*5
—
—
ns
Low V
CC
Data Retention Timing Waveform
V
V
CC
CS
Data retention mode
t
R
4.5V
DR
2.2V
0V
CS > V - 0.2V
CDR
t
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