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參數(shù)資料
| 型號： | HM62256BLP10 |
| 英文描述： | IC-256K CMOS SRAM |
| 中文描述： | 集成電路- 256K CMOS SRAM的 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大小： | 143K |
| 代理商： | HM62256BLP10 |
HM62256B Series
7
AC Characteristics
(Ta = 0 to +70
°
C, V
CC
= 5 V
±
10%, unless otherwise noted.)
Test Conditions
Input pulse levels: 0.8 V to 2.4 V
Input rise and fall times: 5 ns
Input and output timing reference level: 1.5 V
Output load: HM62256B-4:
HM62256B-5:
HM62256B-7/8: 1 TTL Gate + C
L
(100 pF)(Including scope & jig)
1 TTL Gate + C
L
(30 pF)(Including scope & jig)
1 TTL Gate + C
L
(50 pF)(Including scope & jig)
Read Cycle
HM62256B
-4
-5
-7
-8
Parameter
Symbol
Min Max Min
Max Min Max Min
Max Unit
Notes
Read cycle time
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
45
—
55
—
70
—
85
—
ns
Address access time
—
45
—
55
—
70
—
85
ns
Chip select access time
—
45
—
55
—
70
—
85
ns
Output enable to output valid
30
—
35
—
40
—
45
ns
Chip selection to output in low-Z
5
—
5
—
10
—
10
—
ns
2
Output enable to output in low-Z
5
—
5
—
5
—
5
—
ns
2
Chip deselection in to output in
high-Z
0
20
0
20
0
25
0
30
ns
1, 2
Output disable to output in high-Z
t
OHZ
t
OH
0
20
0
20
0
25
0
30
ns
1, 2
Output hold from address change
Notes: 1. t
and t
defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
5
—
5
—
5
—
10
—
ns
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| HM62256BLP12U | IC-256K CMOS SRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM62256BLP12U | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:IC-256K CMOS SRAM |
| HM62256BLP7 | 制造商:Hitachi 功能描述: |
| HM62256BLP-7 | 制造商:hitachi 功能描述: 制造商:HITCHI 功能描述: |
| HM62256BLP-7SL | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:256k SRAM (32-kword x 8-bit) |
| HM62256BLPI-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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