參數(shù)資料
型號(hào): HM62256B
廠商: Hitachi,Ltd.
英文描述: Triple 3-Input Positive-NAND Gates 20-LCCC -55 to 125
中文描述: 256k的SRAM(32 KWord的× 8位)
文件頁數(shù): 1/20頁
文件大小: 154K
代理商: HM62256B
HM62256B Series
256k SRAM (32-kword
×
8-bit)
ADE-203-135F (Z)
Rev. 6.0
Nov. 13, 1997
Description
The Hitachi HM62256B Series is a CMOS static RAM organized 32,768-word
×
8-bit. It realizes higher
performance and low power consumption by employing 0.8
μ
m Hi-CMOS process technology. The
device, packaged in 8
×
14 mm TSOP, 8
×
13.4 mm TSOP with thickness of 1.2 mm, 450 mil SOP (foot
print pitch width), 600 mil plastic DIP, or 300 mil plastic DIP, is available for high density mounting. It
offers low power standby power dissipation; therefore, it is suitable for battery backup systems.
Features
Single 5.0 V supply: 5.0 V
±
10%
Access time: 55 ns/70 ns/85 ns (max)
Power dissipation:
Active: 25 mW (typ) (f = 1 MHz)
Standby: 1.0
μ
W (typ)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Common data input and output
Three state output
Directly TTL compatible all inputs and outputs
Battery backup operation
相關(guān)PDF資料
PDF描述
HM62256BLP-7SL Triple 3-Input Positive-NAND Gates 14-CDIP -55 to 125
HM62256BLSP-7 Triple 3-Input Positive-NAND Gates 14-CFP -55 to 125
HM62256BLSP-7SL Triple 3-Input Positive-AND Gates 14-CDIP -55 to 125
HM62256BLT-7SL Triple 3-Input Positive-AND Gates 14-CFP -55 to 125
HM62256BLT-8 Triple 3-Input Positive-AND Gates 14-CDIP -55 to 125
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