參數(shù)資料
型號: HM62256ALP-10SL
廠商: Hitachi,Ltd.
英文描述: Hex Inverters With Open-Collector Outputs 14-CDIP -55 to 125
中文描述: 32,768字× 8位高速CMOS靜態(tài)RAM
文件頁數(shù): 11/11頁
文件大小: 71K
代理商: HM62256ALP-10SL
Low V
CC
Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed only for L/L-SL version.
Parameter
———————————————————————————————————————————————–
V
CC
for data retention
V
DR
2
———————————————————————————————————————————————–
Data retention current
I
CCDR
——————————————–
———————————————————————————————————————————————–
Chip deselect to data retention time t
CDR
0
——————————————————————————————————––
Operation recovery time
t
R
———————————————————————————————————————————————–
Symbol Min
Typ
*1
Max
Unit
Test conditions
V
CS
V
CC
– 0.2 V, Vin
0 V
0.2
30
*2
μA
V
CC
= 3.0 V, Vin
0 V
0.2
10
*3
μA
CS
V
CC
– 0.2 V
ns
See retention waveform
t
RC*4
ns
Low V
CC
Data Retention Timing Waveform
CC
4.5 V
V
2.2 V
DR
V
0 V
CS
t
CDR
t
R
CS V – 0.2 V
Data retention mode
Notes: 1
Typical values are at V
CC
= 3.0 V, Ta = +25°C and not guaranteed.
20 μA max at Ta = 0 to +40°C. (only for L-version)
3 μA max at Ta = 0 to +40°C. (only for L-SL version)
t
RC
= read cycle time.
CS
controls address buffer,
WE
buffer,
OE
buffer, and Din buffer. If
CS
controls data
retention mode, Vin levels (address,
WE
,
OE
, I/O) can be in the high impedance state.
2.
3.
4.
5.
11
HM62256A Series
HM62256A Series
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PDF描述
HM62256ALP-12 Hex Inverters With Open-Collector Outputs 20-LCCC -55 to 125
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