參數(shù)資料
型號: HM6207P-45
英文描述: x1 SRAM
中文描述: x1的SRAM
文件頁數(shù): 8/11頁
文件大?。?/td> 147K
代理商: HM6207P-45
HM6207H Series
8
Write Timing Waveform (2)
(
&(
Controlled)
t
WC
t
AS
t
CW
t
WP
t
DW
t
DH
Valid Data
Din
Address
CS
WE
t
AW
t
WR
t
WZ
Dout
High impedance
Data undefined
Notes: 1.
2.
3.
4.
A write occurs during the overlap of a low CS and a low WE.
t
WR
is measured from the earlier of CS or WE going high to the end of the
write cycle.
If the CS low transition occurs simultaneously with the WE low transition,
the output buffers remain in a high impedance state.
Dout has the same phase as write data in this write cycle, if t
WR
is long enough.
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