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參數(shù)資料
| 型號： | HM5425161B |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 256M SSTL_2 interface DDR SDRAM(256M SSTL_2接口 DDR 同步DRAM) |
| 中文描述： | 256M DDR SDRAM的接口SSTL_2（256M SSTL_2接口的DDR同步DRAM）的 |
| 文件頁數(shù)： | 14/62頁 |
| 文件大?。?/td> | 1016K |
| 代理商： | HM5425161B |
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HM5425161B, HM5425801B, HM5425401B Series
14
CKE Truth Table
CKE
Current state
Command
n – 1
n
CS
RAS
CAS
WE
Address Notes
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
×
×
×
×
×
×
×
×
2
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
2
Idle
Power down entry (PDEN)
H
L
L
H
H
H
H
L
H
×
×
×
Self refresh
Self refresh exit (SELFX)
L
H
L
H
H
H
L
H
H
×
×
×
Power down
Power down exit (PDEX)
L
H
L
H
H
H
L
H
H
×
×
×
Notes: 1. H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
.
2. All the banks must be in IDLE before executing this command.
3. The CKE level must be kept for 1 CLK cycle (= t
CKEPW
) at least.
Auto-refresh command [REF]:
This command executes auto-refresh. The banks and the ROW addresses
to be refreshed are internally determined by the internal refresh contoroller. The average refresh cycle is 7.8
μ
s. The output buffer becomes High-Z after auto-refresh start. Precharge has been completed automatically
after the auto-refresh. The ACTV or MRS command can be issued t
RFC
after the last auto-refresh command.
Self-refresh entry [SELF]:
This command starts self-refresh. The self-refresh operation continues as long
as CKE is held Low. During the self-refresh operation, all ROW addresses are repeated refreshing by the
internal refresh contoroller. A self-refresh is terminated by a self-refresh exit command.
Power down mode entry [PDEN]:
t
PDEN
(= 1 cycle) after the cycle when [PDEN] is issued. The DDR
SDRAM enters into power-down mode. In power down mode, power consumption is suppressed by
deactivating the input initial circuit. Power down mode continues while CKE is held Low. No internal
refresh operation occurs during the power down mode. [PDEN] do not disable DLL.
Self-refresh exit [SELFX]:
This command is executed to exit from self-refresh mode. 10 cycles (= t
SNR
)
after [SELFX], non-read commands can be executed. For read operation, wait for 200 cycles (= t
SRD
) after
[SELFX] to adjust Dout timing by DLL. After the exit, within 7.8
μ
s input auto-refresh command.
Power down exit [PDEX]:
The DDR SDRAM can exit from power down mode t
PDEX
(1 cycle min.) after the
cycle when [PDEX] is issued.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5425161B/801B/401B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Series 256M SSTL-2 Interface DDR SDRAM 143 MHz/133 MHz/125 |
| HM5425161BTT-10 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| HM5425161BTT-75A | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| HM5425161BTT-75B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
| HM5425401B | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank |
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