參數(shù)資料
型號: HM5225805BTT-75
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
中文描述: 32M X 8 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù): 10/63頁
文件大?。?/td> 462K
代理商: HM5225805BTT-75
HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Data Sheet E0082H10
10
V
SS
and V
SS
Q (power supply pins):
Ground is connected. (V
SS
is for the internal circuit and V
SS
Q is for the
output buffer.)
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the
CS
,
RAS
,
CAS
,
WE
and address pins.
CKE
Command
Symbol
n - 1 n
CS
RAS
CAS WE
BA0/BA1
A10
A0
to A12
Ignore command
DESL
H
×
×
×
×
×
×
×
×
×
H
×
×
×
×
×
×
×
×
×
No operation
NOP
H
L
H
H
H
Column address and read command READ
H
L
H
L
H
V
L
V
Read with auto-precharge
READ A
H
L
H
L
H
V
H
V
Column address and write command WRIT
H
L
H
L
L
V
L
V
Write with auto-precharge
WRIT A
H
L
H
L
L
V
H
V
Row address strobe and bank active ACTV
H
L
L
H
H
V
V
V
Precharge select bank
PRE
H
L
L
H
L
V
L
×
×
×
Precharge all bank
PALL
H
L
L
H
L
×
×
H
Refresh
REF/SELF H
V
L
L
L
H
×
Mode register set
Note:
H: V
IH
. L: V
IL
.
×
: V
IH
or V
IL
. V: Valid address input
MRS
H
×
L
L
L
L
V
V
V
Ignore command [DESL]:
When this command is set (
CS
is High), the SDRAM ignore command input at
the clock. However, the internal status is held.
No operation [NOP]:
This command is not an execution command. However, the internal operations
continue.
Column address strobe and read command [READ]:
This command starts a read operation. In addition,
the start address of burst read is determined by the column address (AY0 to AY8; HM5225165B, AY0 to
AY9; HM5225805B, AY0 to AY9, AY11; HM5225405B) and the bank select address (BS). After the read
operation, the output buffer becomes High-Z.
Read with auto-precharge [READ A]:
This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4 or 8.
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HM5225405BTT-75 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
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HM5225805BTT-A6 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM
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