- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370620 > HM5212805F (Hitachi,Ltd.) 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM) PDF資料下載
參數(shù)資料
| 型號： | HM5212805F |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM) |
| 中文描述： | 128M的LVTTL接口的SDRAM（128M的LVTTL接口同步的DRAM） |
| 文件頁數(shù)： | 30/63頁 |
| 文件大?。?/td> | 858K |
| 代理商： | HM5212805F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁
HM5212165F/HM5212805F-75/A60/B60
30
Read with auto precharge to Read command interval
1. Different bank:
When some banks are in the active state, the second read command (another bank) is
executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by
the second command is valid. The internal auto-precharge of one bank starts at the next clock of the second
command.
Read with Auto Precharge to Read Command Interval
(Different bank)
CLK
Command
BS
Dout
READ A
READ
out A0
out A1
out B0
out B1
CAS
Latency = 3
Burst Length = 4
bank0
Read A
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by " ".
2. Same bank:
The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank:
When some banks are in the active state, the second write command (another bank) is
executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of
one bank starts at the next clock of the second command .
Write with Auto Precharge to Write Command Interval
(Different bank)
CLK
Command
BS
Din
WRIT A
WRIT
in B1
in B2
in B3
in A0
in A1
in B0
Burst Length = 4
bank0
Write A
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by " ".
2. Same bank:
The consecutive write command (the same bank) is illegal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM5212165F | 128M LVTTL interface SDRAM(128M LVTTL 接口同步DRAM) |
| HM5225165BTT-75 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225805BLTT-A6 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405B-B6 | 256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM |
| HM5225405BLTT-75 | POT 20K OHM 9MM HORZ NO BUSHING |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM5212805FLTD-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5212805FLTD-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212805FLTD-B60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
| HM5212805FTD-75 | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword × 16-bit × 4-bank/4-Mword × 8-bit × 4-bank PC/133, PC/100 SDRAM |
| HM5212805FTD-A60 | 制造商:HITACHI 制造商全稱:Hitachi Semiconductor 功能描述:128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword X 16-bit X 4-bank/4-Mword X 8-bit X 4-bank PC/133, PC/100 SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。