- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370620 > HM51W18165LTT-5 (Hitachi,Ltd.) 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh PDF資料下載
參數(shù)資料
| 型號： | HM51W18165LTT-5 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| 中文描述： | 16米EDO公司的DRAM（1 - Mword 16位）4畝刷新/ 1畝刷新 |
| 文件頁數(shù)： | 6/36頁 |
| 文件大?。?/td> | 461K |
| 代理商： | HM51W18165LTT-5 |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
HM51W16165 Series, HM51W18165 Series
6
RAS
LCAS
UCAS
WE
OE
Output
Operation
H
D
D
D
D
Open
Standby
L
L
H
H
L
Valid
Lower byte Read cycle
L
H
L
H
L
Valid
Upper byte
L
L
L
H
L
Valid
Word
L
L
H
L*
2
D
Open
Lower byte Early write cycle
L
H
L
L*
2
D
Open
Upper byte
L
L
L
L*
2
D
Open
Word
L
L
H
L*
2
H
Undefined
Lower byte Delayed write cycle
L
H
L
L*
2
H
Undefined
Upper byte
L
L
L
L*
2
H
Undefined
Word
L
L
H
H to L
L to H
Valid
Lower byte Read-modify-write cycle
L
H
L
H to L
L to H
Valid
Upper byte
L
L
L
H to L
L to H
Valid
Word
L
H
H
D
D
Open
Word
RAS
-only refresh cycle
CAS
-before-
RAS
refresh cycle or
H to L
H
L
D
D
Open
Word
H to L
L
H
D
D
Open
Word
Self refresh cycle (L-version)
H to L
L
L
D
D
Open
Word
L
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. t
WCS
≥
0 ns Early write cycle
t
WCS
< 0 ns Delayed write cycle
3. Mode is determined by the OR function of the
UCAS
and
LCAS
. (Mode is set by the earliest of
UCAS
and
LCAS
active edge and reset by the latest of
UCAS
and
LCAS
inactive edge.)
However write OPERATION and output HIZ control are done independently by each
UCAS
,
LCAS
.
ex. if
RAS
= H to L,
UCAS
= H,
LCAS
= L, then
CAS
-before-
RAS
refresh cycle is selected.
L
L
H
H
Open
Read cycle (Output disabled)
This Material Copyrighted By Its Respective Manufacturer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM51W16165 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| HM51W16165J-5 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| HM51W16165LTT-6 | x16 EDO Page Mode DRAM |
| HM51W16165LTT-7 | Plastic internal molding, Noise prevention, Small and lightweight interface; HRS No: 112-3433-2 00; Contact Mating Area Plating: Tin |
| HM51W18165LTT-6 | x16 EDO Page Mode DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HM51W18165LTT6 | 制造商:HITACHI 功能描述:* |
| HM51W4260CLTT-6 | 制造商:Hitachi 功能描述: |
| HM5212165/2805 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Series 128M LVTTL Interface SDRAM 66 MHz 2-Mword X 16-Bit X4-Bank |
| HM5212165D/2805D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Series 128M LVTTL Interface SDRAM 100 MHz 2-Mword X 16-Bit X 4- |
| HM5212165D/2805D-B60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128M LVTTL Interface SDRAM 100 MHz 2-Mword X 16-Bit X 4-Ban |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。