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參數(shù)資料
| 型號： | HM51W16165J-5 |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
| 中文描述： | 16米EDO公司的DRAM（1 - Mword 16位）4畝刷新/ 1畝刷新 |
| 文件頁數(shù)： | 16/36頁 |
| 文件大?。?/td> | 461K |
| 代理商： | HM51W16165J-5 |
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HM51W16165 Series, HM51W18165 Series
16
21.t
ASC
, t
CAH
, t
RCS
, t
WCS
, t
WCH
, t
CSR
and t
RPC
are determined by the earlier falling edge of
UCAS
or
LCAS
.
22.t
CRP
, t
CHR
, t
RCH
, t
CPA
and t
CPW
are determined by the later rising edge of
UCAS
or
LCAS
.
23.t
CWL
, t
DH
, t
DS
and t
CHS
should be satisfied by both
UCAS
and
LCAS
.
24.t
CP
is determined by the time that both
UCAS
and
LCAS
are high.
25.t
(min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode
RAS
cycle (EDO
page mode mix cycle (1), (2)), minimum value of
CAS
cycle (t
+ t
+ 2 t
) becomes greater
than the specified t
(min) value. The value of
CAS
cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
26.When output buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large V
CC
/V
SS
line noise, which causes to degrade V
IH
min/V
IL
max level.
27.Data output turns off and becomes high impedance from later rising edge of
RAS
and
CAS
.
Hold time and turn off time are specified by the timing specifications of later rising edge of
RAS
and
CAS
between t
OHR
and t
OH
, and between t
OFR
and t
OFF
.
28.Please do not use t
timing, 10
μ
s
≤
t
≤
100
μ
s. During this period, the device is in
transition state from normal operation mode to self refresh mode. If t
RASS
≥
100
μ
s, then
RAS
precharge time should use t
RPS
instead of t
RP
.
29.If you use distributed CBR refresh mode with 15.6
μ
s interval in normal read/write cycle, CBR
refresh should be executed within 15.6
μ
s immediately after exiting from and before entering
into self refresh mode.
30.If you use
RAS
only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 1024
cycles (4096 cycles: HM51W16165 Series, 1024 cycles: HM51W18165 Series) of distributed
CBR refresh with 15.6
μ
s interval should be executed within 64 or 16 ms (64 ms: HM51W16165,
16 ms: HM51W18165) immediately after exiting from and before entering into the self refresh
mode.
31.Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
32.XXX: H or L (H: V
IH
(min)
≤
V
IN
≤
V
IH
(max), L: V
IL
(min)
≤
V
IN
≤
V
IL
(max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
be applied V
IH
or V
IL
.
This Material Copyrighted By Its Respective Manufacturer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HM51W16165LTT-6 | x16 EDO Page Mode DRAM |
| HM51W16165LTT-7 | Plastic internal molding, Noise prevention, Small and lightweight interface; HRS No: 112-3433-2 00; Contact Mating Area Plating: Tin |
| HM51W18165LTT-6 | x16 EDO Page Mode DRAM |
| HM51W18165LTT-7 | x16 EDO Page Mode DRAM |
| HM51W18165J-5 | 16 M EDO DRAM (1-Mword 16-bit) 4 k Refresh/1 k Refresh |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HM51W17805J-6GS | 制造商:Hitachi 功能描述: |
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| HM51W18165LTT6 | 制造商:HITACHI 功能描述:* |
| HM51W4260CLTT-6 | 制造商:Hitachi 功能描述: |
| HM5212165/2805 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Series 128M LVTTL Interface SDRAM 66 MHz 2-Mword X 16-Bit X4-Bank |
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