參數(shù)資料
型號(hào): HM5164165FJ-6
廠商: Hitachi,Ltd.
英文描述: 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
中文描述: 6400 EDO公司的DRAM(4 Mword x 16位)8K的refresh/4k刷新
文件頁(yè)數(shù): 16/37頁(yè)
文件大小: 510K
代理商: HM5164165FJ-6
HM5164165F Series, HM5165165F Series
16
Refresh
(HM5165165F Series)
Parameter
Symbol
Max
Unit
Note
Refresh period
t
REF
64
ms
4096 cycles
Self Refresh Mode
(L-version)
HM5164165FL/HM5165165FL
-5
-6
Parameter
RAS
pulse width (self refresh)
RAS
precharge time (self refresh)
CAS
hold time (self refresh)
Notes: 1. AC measurements assume t
T
= 2 ns.
2. An initial pause of 200
μ
s is required after power up followed by a minimum of eight initialization
cycles (any combination of cycles containing
RAS
-only refresh or
CAS
-before-
RAS
refresh).
3. Operation with the t
(max) limit insures that t
(max) can be met, t
(max) is specified as a
reference point only; if t
is greater than the specified t
RCD
(max) limit, than the access time is
controlled exclusively by t
CAC
.
4. Operation with the t
(max) limit insures that t
(max) can be met, t
(max) is specified as a
reference point only; if t
is greater than the specified t
RAD
(max) limit, then access time is
controlled exclusively by t
AA
.
5. Either t
OED
or t
CDD
must be satisfied.
6. Either t
DZO
or t
DZC
must be satisfied.
7. V
(min) and V
(max) are reference levels for measuring timing of input signals. Also, transition
times are measured between V
IH
(min) and V
IL
(max).
8. Assumes that t
t
(max) and t
t
RAD
(max). If t
or t
is greater than the maximum
recommended value shown in this table, t
RAC
exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
10.Assumes that t
RCD
t
RCD
(max) and t
RCD
+ t
CAC
(max)
t
RAD
+ t
AA
(max).
11.Assumes that t
RAD
t
RAD
(max) and t
RCD
+ t
CAC
(max)
t
RAD
+ t
AA
(max).
12.Either t
RCH
or t
RRH
must be satisfied for a read cycles.
13.t
(max), t
(max), t
(max) and t
(max) define the time at which the outputs achieve the
open circuit condition and are not referred to output voltage levels.
14.t
, t
, t
, t
and t
are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only; if t
t
(min), the cycle is an early write cycle and the
data out pin will remain open circuit (high impedance) throughout the entire cycle; if t
RWD
t
RWD
(min), t
t
(min), and t
t
(min), or t
t
(min), t
t
(min) and t
t
(min), the cycle is a read-modify-write and the data output will contain data read from the selected
cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access
time) is indeterminate.
15.t
and t
are referred to
UCAS
and
LCAS
leading edge in early write cycles and to
WE
leading
edge in delayed write or read-modify-write cycles.
Symbol
Min
Max
Min
Max
Unit
Notes
t
RASS
t
RPS
t
CHS
100
100
μ
s
25
90
110
ns
25
–50
–50
ns
29
相關(guān)PDF資料
PDF描述
HM5164165FLJ-5 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5164165FLJ-6 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5164165FTT-5 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5165165FTT-5 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
HM5164165FTT-6 64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
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