7
HLX6228
WRITE CYCLE AC TIMING CHARACTERISTICS (1, 2)
(1) Key Note: This part must be Write controlled using the NCS pin: it requires that NCS returns to a high state for at least 5ns whenever there is an
address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched.
The part must be controlled in this fashion to meet the timing specifications defined.
(2) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the
Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ.
(3) Typical operating conditions: VDD=3.3 V, TA=25
°
C, pre-radiation.
(4) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55 to 125
°
C, post total dose at 25
°
C.
(5) TAVAVW = TWLWH + TWHWL
(6) Guaranteed but not tested.
Symbol
Parameter
Typical
(3)
-55 to 125
°
C
Min
30
Units
Worst Case (4)
TAVAVW
Write Cycle Time
(5)
25
25
20
25
0
0
0
0
12
5
5
25
ns
TWLWH
Write Enable Write Pulse Width
ns
TSLWH
Chip Select to End of Write Time
ns
TDVWH
Data Valid to End of Write Time
ns
TAVWH
Address Valid to End of Write Time
ns
TWHDX
Data Hold Time after End of Write Time
ns
TAVWL
Address Valid Setup to Start of Write Time
ns
TWHAX
Address Valid Hold after End of Write Time
ns
TWLQZ
Write Enable to Output Disable Time
ns
TWHQX
Write Disable to Output Enable Time
ns
TWHWL
Write Disable to Write Enable Pulse Width (6)
ns
TEHWH
Chip Enable to End of Write Time
ns
Max
ADDRESS
HIGH
IMPEDANCE
DATA OUT
NWE
DATA IN
DATA VALID
T
AVAVW
NCS
CE
T
AVWH
T
WLWH
T
AVWL
T
WLQZ
T
DVWH
T
WHQX
T
WHDX
T
SLWH
T
EHWH
T
WHAX
T
WHWL