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參數(shù)資料
| 型號(hào)： | HIP9011ABZT |
| 廠(chǎng)商： | Intersil |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SENSOR ENGINE KNOCK 20-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類(lèi)型： | 引擎敲擊信號(hào)處理器 |
| 輸入類(lèi)型： | 邏輯 |
| 輸出類(lèi)型： | 邏輯 |
| 接口： | SPI |
| 電流 - 電源： | 8mA |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 帶卷 (TR) |
5
FN4367.2
January 6, 2006
Timing Diagrams
FIGURE 1. SPI TIMING
B7
B6
B5
B4
B3
B2
B1
B0
SI
SCK
CS
tCSCH
tCSCF
tPWH
tPWL
tSCCH
tSUH
tHH
INT/HOLD
tCIH
B7
B6
B5
B4
B3
B2
B1
B0
SO
tCSH
TABLE 1. SPI TIMING REQUIREMENTS
SYMBOL
REQUIREMENT
TIME
tCSCH
Minimum time from CS falling edge to SCK rising edge.
10ns
tCSCF
Minimum time from CS falling edge to SCK falling edge.
80ns
tPWL
Minimum time for the SCK low.
60ns
tPWH
Minimum time for the SCK high.
60ns
tSCCH
Minimum time from SCK falling after 8 bits to CS raising edge.
80ns
tSUH
Minimum time from data high to falling edge of spiclk.
20ns
tSUL
Minimum time from data low to falling edge of spiclk.
20ns
tHH
Minimum time for data high after the falling edge of the spiclk.
10ns
tHL
Minimum time for data low after the falling edge of the spiclk.
10ns
tCIH
Minimum time after CS raises until INT/HOLD goes high.
8
s
tCSH
Minimum time between programming 2 internal registers.
200ns
INT/HOLD
INTOUT
t1
t2
t3
t4
FIGURE 2. INTEGRATOR TIMING
TABLE 2. INTEGRATE/HOLD TIMING REQUIREMENTS
SYMBOL
REQUIREMENT
TIME
t1
Maximum rise time of the INT/HOLD signal.
45ns
t2
Maximum time after INT/HOLD rises for INTOUT to begin to integrate.
20
s
t3
Maximum fall time of INT/HOLD signal.
45ns
t4
Typical time after INT/HOLD goes low before chip goes into hold state.
20
s
HIP9011
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