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參數(shù)資料
| 型號： | HI7190IP |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT PROGBL SER 20-PDIP |
| 標(biāo)準包裝： | 18 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 32.5mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
17
FN3612.10
June 27, 2006
DRDY - Data Ready. This is an output status flag from the
device to signal that the Data Output Register has been
updated with the new conversion result. DRDY is useful as an
edge or level sensitive interrupt signal to a microprocessor or
microcontroller. DRDY low indicates that new data is available
at the Data Output Register. DRDY will return high upon
completion of a complete Data Output Register read cycle.
MODE - Mode. This input is used to select between
Synchronous Self Clocking Mode (‘1’) or the Synchronous
External Clocking Mode (‘0’). When this pin is tied to VDD the
serial port is configured in the Synchronous Self Clocking
mode where the synchronous shift clock (SCLK) for the serial
port is generated by the HI7190 and has a frequency of
OSC1/8. When the pin is tied to DGND the serial port is
configured for the Synchronous External Clocking Mode
where the synchronous shift clock for the serial port is
generated by an external device up to a maximum frequency
of 5MHz.
Programming the Serial Interface
It is useful to think of the HI7190 interface in terms of
communication cycles. Each communication cycle happens
in 2 phases. The first phase of every communication cycle
is the writing of an instruction byte. The second phase is
the data transfer as described by the instruction byte. It is
important to note that phase 2 of the communication cycle
can be a single byte or a multi-byte transfer of data. For
example, the 3-byte Data Output Register can be read
using one multi-byte communication cycle rather than three
single-byte communication cycles. It is up to the user to
maintain synchronism with respect to data transfers. If the
system processor “gets lost” the only way to recover is to
and a 3-wire data transfer.
Several formats are available for reading from and writing to
the HI7190 registers in both the 2-wire and 3-wire protocols.
A portion of these formats is controlled by the CR<2:1> (BD
and MSB) bits which control the byte direction and bit order
of a data transfer respectively. These two bits can be written
in any combination but only the two most useful will be
discussed here.
The first combination is to reset both the BD and MSB bits
(BD = 0, MSB = 0). This sets up the interface for descending
byte order and MSB first format. When this combination is
used the user should always write the Instruction Register
such that the starting byte is the most significant byte
address. For example, read three bytes of DR starting with
the most significant byte. The first byte read will be the most
significant in MSB to LSB format. The next byte will be the
next least significant (recall descending byte order) again in
MSB to LSB order. The last byte will be the next lesser
significant byte in MSB to LSB order. The entire word was
read MSB to LSB format.
The second combination is to set both the BD and MSB bits
to 1. This sets up the interface for ascending byte order and
LSB first format. When this combination is used the user
should always write the Instruction Register such that the
starting byte is the least significant byte address. For
example, read three bytes of DR starting with the least
significant byte. The first byte read will be the least
significant in LSB to MSB format. The next byte will be the
next greater significant (recall ascending byte order) again in
LSB to MSB order. The last byte will be the next greater
significant byte in LSB to MSB order. The entire word was
read MSB to LSB format.
After completion of each communication cycle, The HI7190
interface enters a standby mode while waiting to receive a
new instruction byte.
Instruction Byte Phase
The instruction byte phase initiates a data transfer
sequence. The processor writes an 8-bit byte (Instruction
Byte) to the Instruction Register. The instruction byte informs
the HI7190 about the Data transfer phase activities and
includes the following information:
Read or Write cycle
Number of Bytes to be transferred
Which register and starting byte to be accessed
Data Transfer Phase
In the data transfer phase, data transfer takes place as set
by the Instruction Register contents. See Write Operation
and Read Operation sections for detailed descriptions.
INSTRUCTION
BYTE
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE 3
INSTRUCTION
DATA TRANSFER
CYCLE
CS
SDIO
FIGURE 13A. 2-WIRE, 3-BYTE READ OR WRITE TRANSFER
INSTRUCTION
BYTE
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE 3
INSTRUCTION
DATA TRANSFER
CYCLE
CS
SDIO
SDO
FIGURE 13B. 3-WIRE, 3-BYTE READ TRANSFER
HI7190
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