- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371815 > HI5828EVAL2 (Intersil Corporation) 12-Bit, 125+MSPS, CommLink⑩ Dual High Speed CMOS D/A (2.7V-5.5V) PDF資料下載
參數(shù)資料
| 型號： | HI5828EVAL2 |
| 廠商： | Intersil Corporation |
| 英文描述： | 12-Bit, 125+MSPS, CommLink⑩ Dual High Speed CMOS D/A (2.7V-5.5V) |
| 中文描述： | 12位，125 MSPS的，CommLink⑩雙路高速CMOS的D / A（為2.7V至5.5V） |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 119K |
| 代理商： | HI5828EVAL2 |
10
Ground Planes
Separate digital and analog ground planes should be used.
All of the digital functions of the device and their
corresponding components should be located over the
digital ground plane and terminated to the digital ground
plane. The same is true for the analog components and the
analog ground plane. Consult Application Note AN9855.
Noise Reduction
To minimize power supply noise, 0.1
μ
F capacitors should be
placed as close as possible to the converter’s power supply
pins, A
VDD
and D
VDD
. Also, the layout should be designed
using separate digital and analog ground planes and these
capacitors should be terminated to the digital ground for
DV
DD
and to the analog ground for A
VDD
. Additional filtering
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of + 1.2V with a
±
10ppm/
o
C drift coefficient over the full
temperature range of the converter. It is recommended that a
0.1
μ
F capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (18)
selects the reference. The internal reference can be selected
if pin 18 is tied low (ground). If an external reference is
desired, then pin 18 should be tied high (the analog supply
voltage) and the external reference driven into REFIO, pin 17.
The full scale output current of the converter is a function of
the voltage reference used and the value of R
SET
. I
OUT
should be within the 2mA to 20mA range, though operation
below 2mA is possible, with performance degradation.
V
FSADJ
and V
REFIO
will be equivalent except for a small
offset voltage. If the internal reference is used, V
FSADJ
will
equal approximately 1.2V on the FSADJ pin (20). If an
external reference is used, V
FSADJ
will equal the external
reference. The calculation for I
OUT
(Full Scale) is:
I
OUT
(Full Scale) = (V
FSADJ
/R
SET
) X 32.
If the full scale output current is set to 20mA by using the
internal voltage reference (1.2V) and a 1.91k
R
SET
resistor, then the input coding to output current will resemble
the following:
Outputs
The 5 MSBs for each DAC on the HI5828 drive a
thermometer decoder
,
which is a digital decoder that has an
N-bit (5 bits for the HI5828) binary coded input word with
2
N
-1 (31 for the HI5828) output bits, where the number of
output bits that are active correlate directly to the input
binary word. The HI5828 uses a thermometer decoder to
significantly minimize the output glitch energy for each DAC.
I/QOUTA and I/QOUTB are complementary current outputs.
The sum of the two currents is always equal to the full scale
output current minus one LSB. If single ended use is
desired, a load resistor can be used to convert the output
current to a voltage. It is recommended that the unused
output be either grounded or equally terminated. The voltage
developed at the output must not violate the output voltage
compliance range of -0.3V to 1.25V. R
LOAD
(the impedance
loading each current output) should be chosen so that the
desired output voltage is produced in conjunction with the
output full scale current. If a known line impedance is to be
driven, then the output load resistor should be chosen to
match this impedance. The output voltage equation is:
V
OUT
= I
OUT
X R
LOAD
.
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 15/22
and 16/23 will be biased at zero volts. The loading as shown
in Figure 1 will result in a 500mV signal at the output of the
transformer if the full scale output current of the DAC is set to
20mA. V
OUT
= 2 x I
OUT
x R
EQ
, where R
EQ
is ~12.5
.
Allowing the center tap to float will result in identical
transformer output, however the output pins of the DAC will
have positive DC offset. Since the DAC’s output voltage
compliance range is -0.3V to +1.25V, the center tap may
need to be left floating or DC offset in order to increase the
amount of signal swing available. The 50
load on the
output of the transformer represents the spectrum analyzer’s
input impedance.
TABLE 1. INPUT CODING vs OUTPUT CURRENT
INPUT CODE (D11-D0)
I/QOUTA (mA)
I/QOUTB (mA)
11 11111 11111
20
0
10 00000 00000
10
10
00 00000 00000
0
20
PIN 15/22
PIN 16/23
HI5828
V
OUT
= (2 x I
OUT
x R
EQ
)V
100
50
50
50
I/QOUTA
I/QOUTB
FIGURE 1.
R
EQ
IS THE IMPEDANCE
LOADING EACH OUTPUT.
50
REPRESENTS THE
SPECTRUM ANALYZER
HI5828
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI5828IN | 12-Bit, 125+MSPS, CommLink⑩ Dual High Speed CMOS D/A (2.7V-5.5V) |
| HI5828 | 12-Bit, 125+MSPS, CommLink⑩ Dual High Speed CMOS D/A (2.7V-5.5V) |
| HI5860SOICEVAL1 | 12-Bit, 125MSPS, CommLinkTM High Speed D/A Converter |
| HI5860IA | CONNECTOR ACCESSORY |
| HI5860IB | CONNECTOR ACCESSORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5828IN | 功能描述:DAC DUAL 12BIT 130MHZ 48-LQFP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| HI5860 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 125MSPS, CommLinkTM High Speed D/A Converter |
| HI5860 WAF | 制造商:Intersil Corporation 功能描述: |
| HI5860_05 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 130MSPS, High Speed D/A Converter |
| HI5860_08 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:12-Bit, 130MSPS, High Speed D/A Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。