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參數(shù)資料
| 型號(hào)： | HI5741BIBZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV D/A 14BIT 100MSPS 28SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 20ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 650mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 100M |
| 其它名稱： | HI5741BIBZ-TDKR |
3
FN4071.12
September 20, 2006
Absolute Maximum ratings TA =+25°C
Thermal Information
Digital Supply Voltage VCC to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Negative Digital Supply Voltage DVEE to DGND . . . . . . . . . . -5.5V
Negative Analog Supply Voltage AVEE to AGND, ARTN . . . . -5.5V
Digital Input Voltages (D13-D0, CLK) to DGND. . . . . DVCC to -0.5V
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . .
±2.5mA
Voltage from CTRL AMP IN to AVEE. . . . . . . . . . . . . . . . 2.5V to 0V
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . .
±2.5mA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . -3.7V to AVEE
Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature
HI5741BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . .-65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications AVEE, DVEE = -4.94V to -5.46V, VCC = +4.75 to +5.25V, VREF = Internal,
TA = +25°C
PARAMETER
TEST CONDITIONS
HI5741BI
TA = -40°C TO +85°C
UNITS
MIN
TYP
MAX
SYSTEM PERFORMANCE
Resolution
14
-
Bits
Integral Linearity Error, INL
(Note 5)
“Best Fit Straight Line”, TA = +25°C
-1.5
±1.0
1.5
LSB
“Best Fit Straight Line”, TA = -40°C to +85°C
-1.75
-
1.75
LSB
Differential Linearity Error, DNL
-1.0
±0.5
1.0
LSB
Offset Error, IOS
(Note 5)
-
8
75
A
Full Scale Gain Error, FSE
(Notes 3, 5)
-
3.2
10
%
Full Scale Gain Drift
With Internal Reference
-
±150
-
ppm
FSR/°C
Offset Drift Coefficient
(Note 4)
-
0.05
A/°C
Full Scale Output Current, IFS
-
-20.48
-
mA
Output Voltage Compliance Range
(Note 4)
-1.25
-
0
V
DYNAMIC CHARACTERISTICS
Throughput Rate
(Note 4)
100
-
MSPS
Output Voltage Settling Time
(1/16th Scale Step Across Segment)
-
11
-
ns
-
20
-
ns
Singlet Glitch Area, GE (Peak)
-
1
-
pVs
Output Slew Rate
-
1,000
-
V/
s
Output Rise Time
-
675
-
ps
Output Fall Time
-
470
-
ps
Spurious Free Dynamic Range within a Window
(Note 4)
fCLK = 10 MSPS, fOUT = 1.23MHz, 2MHz Span
-
87
-
dBc
fCLK = 20 MSPS, fOUT = 5.055MHz, 2MHz Span
-
77
-
dBc
fCLK = 40 MSPS, fOUT = 16MHz, 10MHz Span
-
75
-
dBc
fCLK = 50 MSPS, fOUT = 10.1MHz, 2MHz Span
-
80
-
dBc
fCLK = 80 MSPS, fOUT = 5.1MHz, 2MHz Span
-
78
-
dBc
fCLK = 100 MSPS, fOUT = 10.1MHz, 2MHz Span
-
79
-
dBc
HI5741
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