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參數(shù)資料
| 型號： | HI5735KCBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | CONV D/A 12BIT 80MSPS 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 設(shè)置時間： | 20ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 650mW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 80M |
9
HI5735
as glitch when changing the DAC output. Units are typically
specified in picoVolt-seconds (pV-s).
Applications
Bipolar Applications
To convert the output of the HI5735 to a bipolar 4V swing, the
following applications circuit is recommended. The reference
can only provide 125
A of drive, so it must be buffered to
create the bipolar offset current needed to generate the -2V
output with all bits “off”. The output current must be converted
to a voltage and then gained up and offset to produce the
proper swing. Care must be taken to compensate for the
voltage swing and error.
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
error in step size between adjacent codes along the
converter’s transfer curve. Ideally, the step size is 1 LSB
from one code to the next, and the deviation from 1 LSB is
known as DNL. A DNL specification of greater than -1 LSB
guarantees monotonicity.
Feedthru, is the measure of the undesirable switching noise
coupled to the output.
Output Voltage Full Scale Settling Time, is the time
required from the 50% point on the clock input for a full scale
step to settle within an
±1/
2 LSB error band.
Output Voltage Small Scale Settling Time, is the time
required from the 50% point on the clock input for a 100mV
step to settle within an 1/2 LSB error band. This is used by
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
Glitch Area, GE, is the switching transient appearing on the
output during a code transition. It is measured as the area
under the curve and expressed as a picoVoltTime
specification (typically pVs).
Differential Gain,
A
V, is the gain error from an ideal sine
wave with a normalized amplitude.
Differential Phase,
Φ, is the phase error from an ideal sine
wave.
Signal to Noise Ratio, SNR, is the ratio of a fundamental to
the noise floor of the analog output. The first 5 harmonics
are ignored, and an output filter of 1/2 the clock frequency is
used to eliminate alias products.
Total Harmonic Distortion, THD, is the ratio of the DAC
output fundamental to the RMS sum of the harmonics. The
first 5 harmonics are included, and an output filter of 1/2 the
clock frequency is used to eliminate alias products.
Spurious Free Dynamic Range, SFDR, is the amplitude
difference from a fundamental to the largest harmonically or
non-harmonically related spur. A sine wave is loaded into
the D/A and the output filtered at 1/2 the clock frequency to
eliminate noise from clocking alias terms.
Intermodulation Distortion, IMD, is the measure of the
sum and difference products produced when a two tone
input is driven into the D/A. The distortion products created
will arise at sum and difference frequencies of the two tones.
IMD can be calculated using the following equation:
(21) IOUT
100MHz
LOW PASS
FILTER
SCOPE
HI5735
64
50
FIGURE 12. GLITCH TEST CIRCUIT
FIGURE 13. MEASURING GLITCH ENERGY
a (mV)
t (ns)
GLITCH ENERGY = (
a x t)/2
HI5735
REF OUT
IOUT
1/2 CA2904
+
-
+
-
+
-
50
5k
1/2 CA2904
5k
60
240
240
HFA1100
VOUT
0.1
F
FIGURE 14. BIPOLAR OUTPUT CONFIGURATION
(21)
(26)
IMD
20Log (RMS of Sum and Difference Distortion Products)
RMS Amplitude of the Fundamental
()
-------------------------------------------------------------------------------------------------------------------------------------------------------.
=
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