參數(shù)資料
型號(hào): HI5728INZ-T
廠商: Intersil
文件頁數(shù): 15/19頁
文件大?。?/td> 0K
描述: IC DAC 10BIT PAR 250M 48LQFP
標(biāo)準(zhǔn)包裝: 1,000
設(shè)置時(shí)間: 35ns
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: *
采樣率(每秒): 125M
5
FN4321.5
January 22, 2010
Pin Descriptions
PIN NO.
PIN NAME
PIN DESCRIPTION
39, 38, 37, 36,
35, 34, 33, 32,
31, 30
QD9 (MSB) Through
QD0 (LSB)
Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q
channel.
1, 2, 3, 4, 5, 6, 7,
46, 47, 48
ID9 (MSB) Through
ID0 (LSB)
Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I
channel.
8
SLEEP
Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep
pin has internal 20A active pull-down current.
15
REFLO
Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable.
23
REFIO
Reference voltage input if internal reference is disabled and reference voltage output if internal reference is
enabled. Use 0.1F cap to ground when internal reference is enabled.
22
FSADJ
Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output
Current Per Channel = 32 x IFSADJ.
14, 24
ICOMP1, QCOMP1
Reduces noise. Connect each to AVDD with 0.1F capacitor near each pin. The ICOMP1 and QCOMP1
pins MUST be tied together externally.
13, 18, 19, 25
AGND
Analog Ground Connections.
17
IOUTB
The complimentary current output of the I channel. Bits set to all 0s gives full scale current.
16
IOUTA
Current output of the I channel. Bits set to all 1s gives full scale current.
20
QOUTB
The complimentary current output of the Q channel. Bits set to all 0s gives full scale current.
21
QOUTA
Current output of the Q channel. Bits set to all 1s gives full scale current.
11, 27
NC
No Connect. Recommended: connect to ground.
12, 26
AVDD
Analog Supply (+2.7V to +5.5V).
10, 28, 41, 44
DGND
Digital Ground.
9, 29, 40, 45
DVDD
Supply voltage for digital circuitry (+2.7V to +5.5V).
43
ICLK
Clock input for I channel. Positive edge of clock latches data.
42
QCLK
Clock input for Q channel. Positive edge of clock latches data.
HI5728
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