- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371814 > HI5721BIP (INTERSIL CORP) 10-Bit, 125 MSPS, High Speed D/A Converter PDF資料下載
參數(shù)資料
| 型號： | HI5721BIP |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | 10-Bit, 125 MSPS, High Speed D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.0045 us SETTLING TIME, 10-BIT DAC, PDIP28 |
| 封裝： | PLASTIC, DIP-28 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 205K |
| 代理商： | HI5721BIP |
3-43
Detailed Description
The HI5721 is a 10-bit, current out D/A converter. The DAC
can convert at 125 MSPS and runs on +5V and -5.2V
supplies. The architecture is an R/2R and segmented
switching current cell arrangement to reduce glitch and
maintain 10-bit linearity without laser trimming. The HI5721
achieves its low power and high speed performance from an
advanced BiCMOS process. The HI5721 consumes 700mW
(typical) and has an improved hold time of only 0.5ns
(typical). The HI5721 is an excellent converter to be used for
communications applications and high performance video
systems.
Digital Inputs
The HI5721 is a TTL/CMOS compatible D/A. The inputs can
be inverted using the INVERT pin. When INVERT is LOW
(‘0’) the input quadrature logic simply passes the data
through unchanged.
When INVERT is HIGH (‘1’) bits D0 (LSB) through D8 are
inverted. D9 is not inverted and can be considered a sign bit
when enabling this quadrature compatible mode. The
INVERT function can simplify the requirements for large sine
wave lookup tables in a Numerically Controlled Oscillator.
The NCO used in a DDS application would only have to
store or generate 90 degrees of information and then use the
INVERT control to control the sign of the output waveform.
Data Buffer/Level Shifters
Data inputs D0 (LSB) through D9 (MSB) are internally
translated from TTL to ECL. The internal latch and switching
current source controls are implemented in ECL technology to
maintain high switching speeds and low noise characteristics.
Decoder/Driver
The architecture employs a split R/2R and Segmented
Current source arrangement. Bits D0 (LSB) through D5
directly drive a typical R/2R network to create the binary
weighted current sources. Bits D6 through D9 (MSB) pass
through a “thermometer” encoder that converters the
incoming data into 15 individual segmented current source
enables. The split architecture helps to improve glitch while
maintaining 10-bit linearity without laser trimming. The worst
case glitch is more constant across the entire output transfer
function.
Clocks and Termination
The internal 10-bit register is updated on the rising edge of the
clock. Since the HI5721 clock rate can run to 125 MSPS, to
minimize reflections and clock noise into the part proper
termination should be used. In PCB layout clock runs should be
kept short and have a minimum of loads. To guarantee
consistent results from board to board, controlled impedance
PCBs should be used with a characteristic line impedance Z
O
of 50
.
To terminate the clock line a shunt terminator to ground is the
most effective type at a 125 MSPS clock rate. A typical value
for termination can be determined by the equation:
R
T
= Z
O
,
for the termination resistor. For a controlled impedance
board with a Z
O
of 50
, the R
T
= 50
. Shunt termination is
best used at the receiving end of the transmission line or as
close to the HI5721 CLK pin as possible.
Rise and Fall times and propagation delay of the line will be
affected by the Shunt Terminator. The terminator can be
connected to DGND.
Noise Reduction
To reduce power supply noise, separate analog and digital
power supplies should be used with 0.1
μ
F and 0.01
μ
F
ceramic capacitors placed as close to the body of the
HI5721 as possible on the analog (AV
EE
) and digital (DV
EE
)
supplies. The analog and digital ground returns should be
connected together back at the device to ensure proper
operation on power up. The V
CC
power pin should be
decoupled with a 0.1
μ
F capacitor.
Reference
The internal reference in the HI5721 is a -1.25V (typical)
bandgap voltage reference with a 100
μ
V/
o
C temperature
drift (typical). The internal reference should be buffered by
the Control Amplifier to provide adequate drive for the
segmented current cells and the R/2R resistor ladder.
Reference Out (REF OUT) should be connected to the
Control Amplifier Input (CTRL AMP IN). The Control
Amplifier Output (CTRL AMP OUT) should be used to drive
the Reference Input (REF IN) and a 0.1
μ
F capacitor to
analog V- (AV
EE
). This improves settling time by decoupling
switching noise from the analog output of the HI5721.
The Full Scale Output Current is controlled by the CTRL
AMP IN pin and the set resistor (R
SET
). The ratio is:
I
OUT
(Full Scale) = (V
CTRL AMP IN
/R
SET
) x 32.
Multiplying Capability
The HI5721 can operate in two different multiplying
configurations. First, using the CTRL AMP IN input pin, a
-0.6V to -1.2V signal can be applied with a bandwidth up to
1MHz. To increase the multiplying bandwidth, the 0.1
μ
F
capacitor connected from REF IN to AV
EE
can be reduced.
R
T
= 50
HI5721
DAC
CLK
Z
O
= 50
FIGURE 18. AC TERMINATION OF THE HI5721 CLOCK LINE
HI5721
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI5728EVAL1 | 10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter |
| HI5728 | 10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter |
| HI5728IN | 10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter |
| HI5731BIB-T | 12-Bit Digital-to-Analog Converter |
| HI5731BIB | 12-Bit, 100 MSPS, High Speed D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5721BIPS2503 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HI5721EVP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HI5721-EVP | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit, 125MSPS, High Speed D/A Converter |
| HI5721-EVS | 制造商:Harris Corporation 功能描述: |
| HI5721TMD/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit Digital-to-Analog Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。