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參數(shù)資料
| 型號(hào)： | HI5714/4CBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8-BIT 40MSPS 24-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 300 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 375mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
| 產(chǎn)品目錄頁面： | 1236 (CN2011-ZH PDF) |
11
Timing Definitions
Aperture Delay: Aperture delay is the time delay between
the external sample command (the rising edge of the clock)
and the time at which the signal is actually sampled. This
delay is due to internal clock path propagation delays.
Aperture Jitter: This is the RMS variation in the aperture
delay due to variation of internal clock path delays.
Data Latency
After the analog sample is taken, the data on the bus is
output at the next rising edge of the clock. This is due to the
output latch of the converter. This delay is specified as the
data latency. After the data latency time, the data
representing each succeeding sample is output at the
following clock pulse. The digital data lags the analog input
by 1 cycle.
Static Performance Definitions
Offset Error and Full-Scale Error use a measured value of
the external voltage reference to determine the ideal plus
and minus full-scale values. The results are all displayed in
LSBs.
Bottom Offset Voltage (VOB)
The first code transition should occur at a level 0.5 LSB
above the negative full-scale. Bottom offset voltage is
defined as the deviation of the actual code transition from
this point.
Top Offset Voltage (VOT)
The last code transition should occur for a analog input that
is 1.5 LSBs below positive full-scale. Top Offset Voltage is
defined as the deviation of the actual code transition from
this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB. The converter is guaranteed to have no
missing codes.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
FIGURE 11. 8-BIT VIDEO COMPONENTS
A/D
D/A
DSP/
P
REFERENCE
ICL8069
AMP
HA5020 (Single)
HA5022 (Dual)
HA5024 (Quad)
HA5013 (Triple)
HFA1105 (Single)
HFA1205 (Dual)
HFA1405 (Quad)
HI5714 (8-Bit)
HSP9501
HSP48410
HSP48908
HSP48901
HSP48212
HSP43881
HSP43168
HI1171 (8-Bit)
CA3338 (8-Bit)
HI5721 (10-Bit)
HA5020 (Single)
HA2842 (Single)
HFA1115 (Single)
HFA1212 (Dual)
HFA1412 (Quad)
CMOS Logic Available in FCT
HSP9501: Programmable Data Buffer
HSP48410: Histogrammer/accumulating Buffer, 10-Bit Pixel Resolution, 4K x 4K Frame Size
HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit
HSP48901: 3 x 3 Image Filter, 30MHz, 8-Bit
HSP48212: Video Mixer
HSP43881: Digital Filter, 30MHz, 1-D and 2-D Fir Filters
HSP43168: Dual Fir Filter, 10-Bit, 33/45MHz
HI3050 (10-Bit)
HI5714
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5714-6CB | 制造商:Intersil Corporation 功能描述: |
| HI5714EVAL | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 HI5714 EVAL PL ATFORM RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| HI5721 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit, 125 MSPS, High Speed D/A Converter |
| HI5721 WAF | 制造商:Harris Corporation 功能描述: |
| HI5721_03 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit, 125MSPS, High Speed D/A Converter |
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