- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383057 > HI5703KCB (INTERSIL CORP) 10-Bit, 40 MSPS A/D Converter PDF資料下載
參數(shù)資料
| 型號(hào)： | HI5703KCB |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | ADC |
| 英文描述： | 10-Bit, 40 MSPS A/D Converter |
| 中文描述： | 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, MS-013AE, SOIC-28 |
| 文件頁(yè)數(shù)： | 12/18頁(yè) |
| 文件大小： | 181K |
| 代理商： | HI5703KCB |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)當(dāng)前第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)
4-12
Detailed Description
Theory of Operation
The HI5703 is a 10-bit fully differential sampling pipeline A/D
converter with digital error correction. Figure 15 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal
,
φ
1
and
φ
2
, derived from the master clock. During the sampling
phase,
φ
1
, the input signal is applied to the sampling
capacitors, C
S
. At the same time the holding capacitors, C
H
,
are discharged to analog ground. At the falling edge of
φ
1
the input signal is sampled on the bottom plates of the
sampling capacitors. In the next clock phase,
φ
2
, the two
bottom plates of the sampling capacitors are connected
together and the holding capacitors are switched to the op-
amp output nodes. The charge then redistributes between
C
S
and C
H
completing one sample-and-hold cycle. The
output is a fully-differential, sampled-data representation of
the analog input. The circuit not only performs the sample-
and-hold function but will also convert a single-ended input
to a fully-differential output for the converter core. During the
sampling phase, the V
IN
pins see only the on-resistance of a
switch and C
S
. The relatively small values of these
components result in a typical full power input bandwidth of
250MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram in Figure 1, nine identical pipeline subconverter
stages, each containing a two-bit flash converter and a two-
bit multiplying digital-to-analog converter, follow the S/H
circuit with the tenth stage being a one bit flash converter.
Each converter stage in the pipeline will be sampling in one
phase and amplifying in the other clock phase. Each
individual subconverter clock signal is offset by 180 degrees
from the previous stage clock signal resulting in alternate
stages in the pipeline performing the same operation.
The two-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant
bits to form the final ten bit output for the converter.
Because of the pipeline nature of this converter, the data on
the bus is output at the 7th cycle of the clock after the analog
sample is taken. This delay is specified as the data latency.
After the data latency time, the data representing each
succeeding sample is output at the following clock pulse.
The output data is synchronized to the external clock by a
double buffered latching technique.
The digital output bits are available in offset binary or two’s
complement format, the format being set by the Data Format
Select (DFS) input.
TABLE 1. PIN DESCRIPTION
PIN #
NAME
DESCRIPTION
1
DV
CC1
Digital Supply (+5.0V)
2
DGND
Digital Ground
3
DV
CC1
Digital Supply (+5.0V)
4
DGND
Digital Ground
5
AV
CC
Analog Supply (+5.0V)
6
AGND
Analog Ground
7
V
REF
+
Positive Reference Voltage Input
8
V
REF
-
Negative Reference Voltage Input
9
V
IN
+
Positive Analog Input
10
V
IN
-
Negative Analog Input
11
V
DC
DC Bias Voltage Output
12
AGND
Analog Ground
13
AV
CC
Analog Supply (+5.0V)
14
OE
Digital Output Enable Control Input
15
DFS
Data Format Select Input
16
D9
Data Bit 9 Output (MSB)
17
D8
Data Bit 8 Output
18
D7
Data Bit 7 Output
19
D6
Data Bit 6 Output
20
D5
Data Bit 5 Output
21
DGND
Digital Ground
22
CLK
Sample Clock Input
23
DV
CC2
Digital Output Supply (+3.3V to +5V)
24
D4
Data Bit 4 Output
25
D3
Data Bit 3 Output
26
D2
Data Bit 2 Output
27
D1
Data Bit 1 Output
28
D0
Data Bit 0 Output (LSB)
-
+
+
-
C
H
C
S
C
S
C
H
V
IN
+
V
OUT+
V
OUT-
V
IN
-
φ
1
φ
1
φ
1
φ
2
φ
1
φ
1
φ
1
FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI5703EVAL | 10-Bit, 40 MSPS A/D Converter |
| HI5710A | 10-Bit, 20 MSPS A/D Converter |
| HI5710AJCQ | Circular Connector; No. of Contacts:32; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:18-32 RoHS Compliant: No |
| HI5714 | 8-Bit, 40/60/75/80 MSPS A/D Converter |
| HI5714EVAL | 8-Bit, 40/60/75/80 MSPS A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5703KCB WAF | 制造商:Harris Corporation 功能描述: |
| HI5703KCB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 10-Bit |
| HI5710A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit, 20 MSPS A/D Converter |
| HI5710A_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit, 20 MSPS A/D Converter |
| HI5710AJCQ | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:10-Bit, 20 MSPS A/D Converter |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。