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參數(shù)資料
| 型號： | HI5675JCB |
| 廠商： | INTERSIL CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 20MSPS, Flash A/D Converter |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大小： | 93K |
| 代理商： | HI5675JCB |
7
Detailed Description
The HI5675 is a 2-step A/D converter featuring a 4-bit upper
comparator group and two lower comparator groups of 4 bits
each. The reference voltage can be obtained from the
onboard bias generator or be supplied externally. This IC uses
an offset canceling type comparator that operates
synchronously with an external clock. The operating modes of
the part are input sampling (S), hold (H), and compare (C).
The operation of the part is illustrated in Figure 2. A
reference voltage that is between V
RT
-V
RB
is constantly
applied to the upper 4-bit comparator group. VI(1) is
sampled with the falling edge of the first clock by the upper
comparator block. The lower block A also samples VI(1) on
the same edge. The upper comparator block finalizes
comparison data MD(1) with the rising edge of the first clock.
Simultaneously the reference supply generates a reference
voltage RV(1) that corresponds to the upper results and
applies it to the lower comparator block A. The lower
comparator block finalizes comparison data LD(1) with the
rising edge of the second clock. MD(1) and LD(1) are
combined and output as OUT(1) with the rising edge of the
third clock. There is a 2.5 cycle clock delay from the analog
input sampling point to the corresponding digital output data.
Notice how the lower comparator blocks A and B alternate
generating the lower data in order to increase the overall A/D
sampling rate.
Power, Grounding, and Decoupling
To reduce noise effects, separate the analog and digital
grounds.
In order to avoid latchup at power up, it is necessary
that AV
DD
and DV
DD
be driven from the same supply.
Bypass both the digital and analog V
DD
pins to their
respective grounds with a ceramic 0.1
μ
F capacitor close to
the pin.
Analog Input
The input capacitance is small when compared with other
flash type A/D converters. However, it is necessary to drive
the input with an amplifier with sufficient bandwidth and drive
capability. In order to prevent parasitic oscillation, it may be
necessary to insert a low value (i.e., 0.24
) resistor between
the output of the amplifier and the A/D input.
Reference Input
The range of the A/D is set by the voltage between V
RT
and
V
RB
. The internal bias generator will set V
RTS
to 2.6V and
V
RBS
to 0.6V. These can be used as the part reference by
shorting V
RT
and V
RTS
and V
RB
to V
RBS
. The analog input
range of the A/D will now be from 0.6V to 2.6V and is
referred to as Self Bias Mode 1. Self Bias Mode 2 is where
VRB is connected to AGND and V
RT
is shorted to V
RTS
.
The analog input range will now be from 0V to 2.4V.
TABLE 1. A/D OUTPUT CODE TABLE
INPUT SIGNAL
VOLTAGE
STEP
DIGITAL OUTPUT CODE
MSB
D6
D5
D4
D3
D2
D1
LSB
V
RT
255
1
1
1
1
1
1
1
1
128
1
0
0
0
0
0
0
0
127
0
1
1
1
1
1
1
1
V
RB
0
0
0
0
0
0
0
0
0
HI5675
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相關代理商/技術參數(shù) |
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|---|---|
| HI-5700 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 20 MSPS Flash A/D Converter |
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| HI-5700883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, 20 MSPS Flash A/D Converter |
| HI-5701 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:6-Bit, 30MSPS, Flash A/D Converter |
| HI-5701/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:6-Bit, 30 MSPS Flash A/D Converter |
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