- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371814 > HI5630CN (Intersil Corporation) Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference PDF資料下載
參數(shù)資料
| 型號(hào)： | HI5630CN |
| 廠商： | Intersil Corporation |
| 英文描述： | Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference |
| 中文描述： | 三8位，80Msps的A / D轉(zhuǎn)換器內(nèi)部電壓基準(zhǔn) |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 125K |
| 代理商： | HI5630CN |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
8
Detailed Description
Theory of Operation
The HI5630 is a triple 8-Bit fully differential sampling pipeline
A/D converter with digital error correction logic. Each of the
three channels are identical so this discussion will only cover
one channel. Figure 3 depicts the circuit for the front end
differential-in-differential-out sample-and-hold (S/H). The
switches are controlled by an internal sampling clock which
is a non-overlapping two phase signal,
Φ
1
and
Φ
2
, derived
from the master sampling clock. During the sampling phase,
Φ
1
, the input signal is applied to the sampling capacitors,
C
S
. At the same time the holding capacitors, C
H
, are
discharged to analog ground. At the falling edge of
Φ
1
the
input signal is sampled on the bottom plates of the sampling
capacitors. In the next clock phase,
Φ
2
, the two bottom
plates of the sampling capacitors are connected together
and the holding capacitors are switched to the op amp
output nodes. The charge then redistributes between C
S
and C
H
completing one sample-and-hold cycle. The front
end sample-and-hold output is a fully-differential, sampled-
data representation of the analog input. The circuit not only
performs the sample-and-hold function but will also convert
a single-ended input to a fully-differential output for the
converter core. During the sampling phase, the V
IN
pins see
only the on-resistance of a switch and C
S
. The relatively
small values of these components result in a typical full
power input bandwidth of 250MHz for the converter.
As illustrated in the functional block diagram and the timing
diagram, identical pipeline subconverter stages, each
containing a two-bit flash converter and a two-bit multiplying
digital-to-analog converter, follow the S/H circuit with the last
stage being a two bit flash converter. Each converter stage
in the pipeline will be sampling in one phase and amplifying
in the other clock phase. Each individual subconverter clock
signal is offset by 180 degrees from the previous stage clock
signal resulting in alternate stages in the pipeline performing
the same operation.
The output of each of the identical two-bit subconverter
stages is a two-bit digital word containing a supplementary
bit to be used by the digital error correction logic. The output
of each subconverter stage is input to a digital delay line
which is controlled by the internal sampling clock. The
function of the digital delay line is to time align the digital
outputs of the identical two-bit subconverter stages with the
corresponding output of the last stage flash converter before
applying the results to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final
ten bit digital data output of the converter.
Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 5th cycle of the clock after the analog
sample is taken. This time delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital output data is
synchronized to the external sampling clock by a double
buffered latching technique. The digital output data is
available in two’s complement or offset binary format
depending on the state of the Data Format Select (DFS)
control input (see Table 1, A/D Code Table).
Internal Reference Voltage Output, V
ROUT
The HI5630 is equipped with an internal reference voltage
generator, therefore, no external reference voltage is
required. V
ROUT
must be connected to V
RIN
when using the
internal reference voltage. An internal band-gap reference
voltage followed by an amplifier/buffer generates the
precision +2.5V reference voltage used by the converter. A
8:1 array of substrate PNPs generates the “delta-V
BE
” and a
two-stage op amp closes the loop to create an internal
+1.25V band-gap reference voltage. This voltage is then
amplified by a wide-band uncompensated operational
amplifier connected in a gain-of-two configuration. An
external, user-supplied, 1
μ
F capacitor connected from the
V
ROUT
output pin to analog ground is used to set the dominant
pole and to maintain the stability of the operational amplifier.
Reference Voltage Input, V
RIN
The HI5630 is designed to accept a +2.5V reference voltage
source at the V
REFIN
input pin. Typical operation of the
converter requires V
RIN
to be set at +2.5V. The HI5630 is
tested with V
RIN
connected to V
ROUT
yielding a fully
differential analog input voltage range of
±
0.5V.
The user does have the option of supplying an external
+2.5V reference voltage. As a result of the high input
impedance presented at the V
RIN
input pin, 3.0k
typically,
the external reference voltage being used is only required to
source 1mA of reference input current. In the situation where
an external reference voltage will be used an external 1
μ
F
capacitor must be connected from the V
ROUT
output pin to
analog ground in order to maintain the stability of the internal
operational amplifier.
In order to minimize overall converter noise it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, V
RIN
.
-
+
+
-
C
H
C
S
C
S
C
H
V
IN+
V
OUT+
V
OUT
-
V
IN
-
Φ
1
Φ
1
Φ
1
Φ
2
Φ
1
Φ
1
Φ
1
FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD
HI5630
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HI5630EVAL | Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference |
| HI5634 | High Performance Programmable Phase-Locked Loop for LCD Applications |
| HI5634CB | High Performance Programmable Phase-Locked Loop for LCD Applications |
| HI5640 | 3.3V Dual 8-Bit， 40 MSPS A/D Converter with Internal Voltage Reference (3 pages) FN4657 |
| HI5640CN | Converter IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HI5630EVAL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference |
| HI5630EVAL1 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple 8-Bit, 80MSPS A/D Converter with Internal Voltage Reference |
| HI5634 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Performance Programmable Phase-Locked Loop for LCD Applications |
| HI5634_00 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Performance Programmable Phase-Locked Loop for LCD Applications |
| HI5634CB | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High Performance Programmable Phase-Locked Loop for LCD Applications |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。