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參數(shù)資料
| 型號： | HI3338KIBZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT CMOS 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 設(shè)置時間： | 20ns |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 100mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 50M |
| 產(chǎn)品目錄頁面： | 1236 (CN2011-ZH PDF) |
5
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 20) through D7 (weighted 27),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of VDD and VSS, are shifted to operate between VDD
and VEE. VEE optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the VDD
and VEE supplies.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
Latch Operation
Data is fed from input to output while LE is low: LE should be
tied low for non-clocked operation.
Non-clocked operation or changing data while LE is low is
not recommended for applications requiring low output
“glitch” energy: there is no guarantee of the simultaneous
changing of input data or the equal propagation delay of all
bits through the converter. Several parameters are given if
the converter is to be used in either of these modes: tD2
gives the delay from the input changing to the output
changing (10%), while tSU2 and tH give the set up and hold
times (referred to LE rising edge) needed to latch data. See
Figures 1 and 2.
Clocked operation is needed for low “glitch” energy use. Data
must meet the given tSU1 set up time to the LE falling edge,
and the tH hold time from the LE rising edge. The delay to
the output changing, tD1, is now referred to the LE falling
edge.
There is no need for a square wave LE clock; LE must only
meet the minimum tW pulse width for successful latch
operation. Generally, output timing (desired accuracy of
settling) sets the upper limit of usable clock frequency.
Output Structure
The latches feed data to a row of high current CMOS drivers,
which in turn feed a modified R2R ladder network.
The “N” channel (pull down) transistor of each driver plus
the bottom “2R” resistor are returned to VREF- this is the
(-) full-scale reference. The “P” channel (pull up) transistor
of each driver is returned to VREF+, the (+) full-scale
reference.
In unipolar operation, VREF- would typically be returned to
analog ground, but may be raised above ground (see
specifications). There is substantial code dependent current
that flows from VREF+ to VREF- (see VREF+ input current in
specifications), so VREF- should have a low impedance path
to ground.
In bipolar operation, VREF- would be returned to a negative
voltage (the maximum voltage rating to VDD must be
observed). VEE, which supplies the gate potential for the
output drivers, must be returned to a point at least as
negative as VREF-. Note that the maximum clocking speed
decreases when the bipolar mode is used.
Static Characteristics
The ideal 8-bit D/A would have an output equal to VREF-
with an input code of 00HEX (zero scale output), and an
output equal to 255/256 of VREF+ (referred to VREF-) with
an input code of FFHEX (full scale output). The difference
between the ideal and actual values of these two parameters
are the OFFSET and GAIN errors, respectively; see
Figure 3.
Pin Descriptions
PIN
NAME
DESCRIPTION
1
D7
Most Significant Bit
2
D6
Input
3D5
Data
4D4
Bits
5
D3
(High = True)
6D2
7D1
8VSS
Digital Ground
9
D0
Least Significant Bit. Input Data Bit
10
VEE
Analog Ground
11
VREF- Reference Voltage Negative Input
12
VOUT
Analog Output
13
VREF+ Reference Voltage Positive Input
14
COMP
Data Complement Control input. Active High
15
LE
Latch Enable Input. Active Low
16
V
DD
Digital Power Supply, +5V
HI3338
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