參數(shù)資料
型號: HI3300IN
廠商: INTERSIL CORP
元件分類: ADC
英文描述: 3V 10-Bit, 20MSPS A/D Converter with Internal Voltage Reference
中文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
封裝: 7 X 7 MM, PLASTIC, LQFP-48
文件頁數(shù): 14/16頁
文件大?。?/td> 174K
代理商: HI3300IN
14
Calibration Function
Activating Startup Calibration
To achieve superior linearity, the HI3300 has a built-in
calibration circuit. Startup calibration must be activated when
the power supply and reference voltage have risen and
stabilized. Care should be taken as only the upper five bits
may be output in the worst case if startup calibration is not
activated.
Startup calibration can be activated either at the rise of the
RESET pin (Pin 15) or at the fall of the CE pin (Pin 24). The
startup calibration activation method for each case is shown
in Figure 3.
As shown in the Figure 3, startup calibration must be
activated after the supply voltage has risen and stabilized
(full scale of 90% or more). After activation, startup
calibration is performed for an interval of about 33,000
clocks. Therefore, care should be taken as the output data
during this interval (about 2.3ms at 14.3MHz) cannot be
used.
Calibration Pulse Supply
The IC’s operating status with changes due to fluctuations in
the supply voltage and ambient temperature during use can
be constantly monitored and then compensated
appropriately by inputting a pulse at regular intervals to the
CAL pin (Pin 41). Figure 4 shows the timing chart.
A. WHEN USING RESET
AVDD
VRT
VRB
[t]
[V]
3
0
H
L
RESET
H
L
CE
STARTUP
CALIBRATION
33,000 CLK
[V]
B. WHEN USING CE
AVDD
VRT
VRB
[t]
3
0
RESET
L
H
L
CE
H
STARTUP
CALIBRATION
FIGURE 3. STARTUP CALIBRATION ACTIVATION METHODS
33,000 CLK
N - 3
7CLOCK
1CLOCK OR MORE
N - 2
N - 1
N
D0 TO D9
CAL
CLK
10ns OR MORE
N +5
FIGURE 4. CALIBRATION TIMING CHART
HI3300
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