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參數(shù)資料
| 型號： | HI3197 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DAC |
| 英文描述： | 10-Bit, 125 MSPS D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.0035 us SETTLING TIME, 10-BIT DAC, PQFP48 |
| 文件頁數(shù)： | 19/25頁 |
| 文件大?。?/td> | 284K |
| 代理商： | HI3197 |
19
FIGURE 12A. BLOCK DIAGRAM (MUX.1B MODE)
FIGURE 12B. TIMING CHART (MUX.1B MODE)
NOTE: In MUX.1B mode, Data A and Data B are internally multiplexed and then the resulting signal can be analog output. The frequency of the
clock is halved by the built-in clock frequency divider circuit. CLK/2 can be reset by the reset signal.
Block Diagram and Timing Charts
(Continued)
R
D
Q
Q
INPUT LATCH A
INPUT LATCH B
MUX
LATCH
DAC
CLK/2
(INTERNAL)
CLK
RESET
INPUT DATA A
INPUT DATA B
ANALOG OUT
N
N - 2
N + 2
N + 4
N + 6
N + 8
N + 1
N - 1
N + 3
N + 5
N + 7
N + 9
N + 1
N
N + 2
N + 3
N + 4
N + 5
CLK
t
H-RST
0
(ACTIVE HIGH)
(ACTIVE LOW)
D-FF OUT
RESET
(ACTIVE HIGH)
CLK/2
(INTERNAL)
INPUT DATA A
t
H
INPUT DATA B
t
DO
1
2
t
S
t
DO
t
PD (B)
t
PD (A)
3
t
PW0
t
PW1
t
S-RST
HI3197
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